From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751164AbdAVEzO (ORCPT ); Sat, 21 Jan 2017 23:55:14 -0500 Received: from mail-pg0-f68.google.com ([74.125.83.68]:33086 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750770AbdAVEzJ (ORCPT ); Sat, 21 Jan 2017 23:55:09 -0500 Date: Sun, 22 Jan 2017 13:45:18 +0900 From: Sergey Senozhatsky To: zhouxianrong Cc: Sergey Senozhatsky , linux-mm@kvack.org, linux-kernel@vger.kernel.org, akpm@linux-foundation.org, sergey.senozhatsky@gmail.com, minchan@kernel.org, ngupta@vflare.org, Mi.Sophia.Wang@huawei.com, zhouxiyu@huawei.com, weidu.du@huawei.com, zhangshiming5@huawei.com, won.ho.park@huawei.com Subject: Re: [PATCH] mm: extend zero pages to same element pages for zram Message-ID: <20170122044518.GB7057@tigerII.localdomain> References: <1483692145-75357-1-git-send-email-zhouxianrong@huawei.com> <1484296195-99771-1-git-send-email-zhouxianrong@huawei.com> <20170121084338.GA405@jagdpanzerIV.localdomain> <84073d07-6939-b22d-8bda-4fa2a9127555@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <84073d07-6939-b22d-8bda-4fa2a9127555@huawei.com> User-Agent: Mutt/1.7.2 (2016-11-26) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On (01/22/17 10:58), zhouxianrong wrote: > 1. memset is just set a int value but i want to set a long value. ah... ok. because you union it with the handle. > 2. using clear_page rather than memset MAYBE due to in arm64 arch > it is a 64-bytes operations. clear_page() basically does memset(), which is quite well optimized. except for arm64, yes. > 6.6.4. Data Cache Zero > > The ARMv8-A architecture introduces a Data Cache Zero by Virtual Address (DC ZVA) instruction. This enables a block of 64 > bytes in memory, aligned to 64 bytes in size, to be set to zero. If the DC ZVA instruction misses in the cache, it clears main > memory, without causing an L1 or L2 cache allocation. > > but i only consider the arm64 arch, other archs need to be reviewed. thaks for the reply. -ss