From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751512AbdA0Ub0 (ORCPT ); Fri, 27 Jan 2017 15:31:26 -0500 Received: from mail-ot0-f194.google.com ([74.125.82.194]:34300 "EHLO mail-ot0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750930AbdA0UaE (ORCPT ); Fri, 27 Jan 2017 15:30:04 -0500 Date: Fri, 27 Jan 2017 14:30:01 -0600 From: Rob Herring To: Marc Zyngier Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Gleixner , Jason Cooper , Mark Rutland , Tsahee Zidenberg , Antoine Tenart , Russell King , =?iso-8859-1?Q?Beno=EEt?= Cousson , Tony Lindgren , Kukjin Kim , Krzysztof Kozlowski , Javier Martinez Canillas , Shawn Guo , Sascha Hauer , Fabio Estevam , Santosh Shilimkar , Matthias Brugger , Simon Horman , Magnus Damm , Heiko Stuebner , Maxime Ripard , Chen-Yu Tsai , arm@kernel.org Subject: Re: [PATCH v2 1/2] dt-bindings: arm,gic: Fix binding example for a virt-capable GIC Message-ID: <20170127203001.qvlgzzrh5hx2pykf@rob-hp-laptop> References: <1485186974-13678-1-git-send-email-marc.zyngier@arm.com> <1485186974-13678-2-git-send-email-marc.zyngier@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1485186974-13678-2-git-send-email-marc.zyngier@arm.com> User-Agent: Mutt/1.6.2-neo (2016-08-21) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 23, 2017 at 03:56:13PM +0000, Marc Zyngier wrote: > The joys of copy/paste: the example of a virtualization capable GIC > in the DT binding was wrong, and propagated to dozens of platforms. > By having a GICC region that is only 4kB (instead of 8kB), we > end-up not being able to access the GICC_DIR register which is on > the second page. > > Oh well. Let's fix the source of the crap before tackling individual > offenders. While we're at it, also fix the compatibility string to > mention "arm,gic-400", which is the name of the actual implementation > of the GICv2 spec. "While we're at it", code for should be in a separate patch. :) I wouldn't really care here, but you are not fixing anything... > > Acked-by: Tony Lindgren > Acked-by: Mark Rutland > Acked-by: Arnd Bergmann > Signed-off-by: Marc Zyngier > --- > Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt > index 5393e2a..a3d51ed 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt > +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt > @@ -107,11 +107,11 @@ Required properties: > Example: > > interrupt-controller@2c001000 { > - compatible = "arm,cortex-a15-gic"; > + compatible = "arm,gic-400"; Which one is correct really depends on the platform. The A15 can have an internal or external (gic-400) GIC. The former string is correct for an A15 with an internal GIC. One such platform is Calxeda midway. Arguably, we should not have arm,gic-400 by itself, but have an SoC specific compatible in case it was integrated in interesting ways. Rob