From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753973AbdA3Rvk (ORCPT ); Mon, 30 Jan 2017 12:51:40 -0500 Received: from foss.arm.com ([217.140.101.70]:48450 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751406AbdA3Rvf (ORCPT ); Mon, 30 Jan 2017 12:51:35 -0500 Date: Mon, 30 Jan 2017 17:49:59 +0000 From: Mark Rutland To: Fu Wei Cc: "Rafael J. Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Lorenzo Pieralisi , Sudeep Holla , Hanjun Guo , linux-arm-kernel@lists.infradead.org, Linaro ACPI Mailman List , Linux Kernel Mailing List , ACPI Devel Maling List , rruigrok@codeaurora.org, "Abdulhamid, Harb" , Christopher Covington , Timur Tabi , G Gregory , Al Stone , Jon Masters , Wei Huang , Arnd Bergmann , Catalin Marinas , Will Deacon , Suravee Suthikulpanit , Leo Duran , Wim Van Sebroeck , Guenter Roeck , linux-watchdog@vger.kernel.org, Tomasz Nowicki , Christoffer Dall , Julien Grall Subject: Re: [PATCH v20 08/17] clocksource/drivers/arm_arch_timer: Rework counter frequency detection. Message-ID: <20170130174958.GA3496@leverpostej> References: <20170118132541.8989-1-fu.wei@linaro.org> <20170118132541.8989-9-fu.wei@linaro.org> <20170124172400.GG7572@leverpostej> <20170125172505.GB29027@leverpostej> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 26, 2017 at 01:49:03PM +0800, Fu Wei wrote: > On 26 January 2017 at 01:25, Mark Rutland wrote: > > On Wed, Jan 25, 2017 at 02:46:12PM +0800, Fu Wei wrote: > >> On 25 January 2017 at 01:24, Mark Rutland wrote: > >> > On Wed, Jan 18, 2017 at 09:25:32PM +0800, fu.wei@linaro.org wrote: > >> >> From: Fu Wei > > For CNT{,EL0}BaseN.CNTFRQ, I am very concerned by the wording in the > > current ARMv8 ARM ARM. This does not match my understanding, nor does it > > match the description in the ARMv7 ARM. I believe this may be a > > documentation error, and I'm chasing that up internally. > > > > Either the currently logic in the driver which attempts to read > > CNT{,EL0}BaseN.CNTFRQ is flawed, or the description in the ARM ARM is > > erroneous. > > Yes, those description did confuse me. :-( > > But according to another document(ARMv8-A Foundation Platform User > Guide ARM DUI0677K), > Table 3-2 ARMv8-A Foundation Platform memory map (continued) > > AP_REFCLK CNTBase0, Generic Timer 64KB S > AP_REFCLK CNTBase1, Generic Timer 64KB S/NS > > Dose it means the timer frame 0 can be accessed in SECURE status only, > and the timer frame 1 can be accessed in both status? That does appear to be what it says. I assume in this case CNTCTLBase.CNTSAR<0> is RES0. > And because Linux kernel is running on Non-secure EL1, so should we > skip "SECURE" timer in Linux? I guess you mean by checking the GTx Common flags, to see if the timer is secure? Yes, we must skip those. Looking further at this, the ACPI spec is sorely lacking any statement as to the configuration of CNTCTLBase.{CNTSAR,CNTTIDR,CNTACR}, so it's not clear if we can access anything in a frame, even if it is listed as being a non-secure timer. I think we need a stronger statement here. Otherwise, we will encounter problems. Linux currently assumes that CNTCTLBase.CNTACR is writeable, given a non-secure frame N. This is only the case if CNTCTLBase.CNTSAR.NS == 1. Thanks, Mark.