[PATCH 0/7] arm64: arch_timer: work around Hisilicon erratum 161010101

[PATCH 0/7] arm64: arch_timer: work around Hisilicon erratum 161010101

[Mark Rutland]

Hi,

These patches are a rework of Ding's v9 series [1], addessing some issues with
code style and the commit logs.

Daniel, are you happy to take a look over these?

Catalin, Will, to minimise conflict with the Falkor erratum workaround, I've
added a preparatory patch that simply widens the silicon-errata kconfig column,
which should be queued before either patch.

Would you be happy with that patch going via both the arm64 tree and the
clocksource tree? We need it via the latter for the Hisilicon erratum 161010101
documentation, unless we split the documentation from the code.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2017-January/481089.html

Ding Tianhong (6):
  arm64: arch_timer: add dt binding for hisilicon-161010101 erratum
  arm64: arm_arch_timer: remove fsl-a008585 parameter
  arm64: arch_timer: introduce generic errata handling infrastructure
  arm64: arch_timer: work around Hisilicon erratum 161010101
  arm64: arch_timer: document Hisilicon erratum 161010101
  arm64: arch timer: Add timer erratum property for Hip05-d02 and
    Hip06-d03

Mark Rutland (1):
  arm64: docs: widen silicon-errata kconfig column

 Documentation/admin-guide/kernel-parameters.txt    |   9 --
 Documentation/arm64/silicon-errata.txt             |  44 +++---
 .../devicetree/bindings/arm/arch_timer.txt         |   6 +
 arch/arm64/boot/dts/hisilicon/hip05.dtsi           |   1 +
 arch/arm64/boot/dts/hisilicon/hip06.dtsi           |   1 +
 arch/arm64/include/asm/arch_timer.h                |  38 ++----
 drivers/clocksource/Kconfig                        |  14 ++
 drivers/clocksource/arm_arch_timer.c               | 151 +++++++++++++++------
 8 files changed, 168 insertions(+), 96 deletions(-)

-- 
1.9.1

[PATCH 1/7] arm64: docs: widen silicon-errata kconfig column

[Mark Rutland]

It turns out that kconfigs for errata we need to handle might end up
being too wide to fit in arm64's existing errata table. We may need to
take errata workarounds (and their associated documentation) via
different trees, and widening the table as required is likely to result
in messy merge conflicts.

We can minimise this messiness by widening the column in a separate
patch as a preparatory step. Thus, only the additional lines should
conflict, which is simple to address.

This patch widens the kconfig column by 10 characters, which is
sufficient to fit upcoming errata workarounds. A whitespace mixup is
also corrected, such that all columns are consistently padded using
tabs.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
---
 Documentation/arm64/silicon-errata.txt | 42 +++++++++++++++++-----------------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 405da11..4a5e6cc 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -42,24 +42,24 @@ file acts as a registry of software workarounds in the Linux Kernel and
 will be updated when new workarounds are committed and backported to
 stable kernels.
 
-| Implementor    | Component       | Erratum ID      | Kconfig                 |
-+----------------+-----------------+-----------------+-------------------------+
-| ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319    |
-| ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319    |
-| ARM            | Cortex-A53      | #824069         | ARM64_ERRATUM_824069    |
-| ARM            | Cortex-A53      | #819472         | ARM64_ERRATUM_819472    |
-| ARM            | Cortex-A53      | #845719         | ARM64_ERRATUM_845719    |
-| ARM            | Cortex-A53      | #843419         | ARM64_ERRATUM_843419    |
-| ARM            | Cortex-A57      | #832075         | ARM64_ERRATUM_832075    |
-| ARM            | Cortex-A57      | #852523         | N/A                     |
-| ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220    |
-| ARM            | Cortex-A72      | #853709         | N/A                     |
-| ARM            | MMU-500         | #841119,#826419 | N/A                     |
-|                |                 |                 |                         |
-| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375    |
-| Cavium         | ThunderX ITS    | #23144          | CAVIUM_ERRATUM_23144    |
-| Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |
-| Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456    |
-| Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
-|                |                 |                 |                         |
-| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585     |
+| Implementor    | Component       | Erratum ID      | Kconfig                          |
++----------------+-----------------+-----------------+----------------------------------+
+| ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319             |
+| ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319             |
+| ARM            | Cortex-A53      | #824069         | ARM64_ERRATUM_824069             |
+| ARM            | Cortex-A53      | #819472         | ARM64_ERRATUM_819472             |
+| ARM            | Cortex-A53      | #845719         | ARM64_ERRATUM_845719             |
+| ARM            | Cortex-A53      | #843419         | ARM64_ERRATUM_843419             |
+| ARM            | Cortex-A57      | #832075         | ARM64_ERRATUM_832075             |
+| ARM            | Cortex-A57      | #852523         | N/A                              |
+| ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220             |
+| ARM            | Cortex-A72      | #853709         | N/A                              |
+| ARM            | MMU-500         | #841119,#826419 | N/A                              |
+|                |                 |                 |                                  |
+| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375             |
+| Cavium         | ThunderX ITS    | #23144          | CAVIUM_ERRATUM_23144             |
+| Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154             |
+| Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456             |
+| Cavium         | ThunderX SMMUv2 | #27704          | N/A                              |
+|                |                 |                 |                                  |
+| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585              |
-- 
1.9.1

[PATCH 2/7] arm64: arch_timer: add dt binding for hisilicon-161010101 erratum

[Mark Rutland]

From: Ding Tianhong <dingtianhong@huawei.com>

This erratum describes a bug in logic outside the core, so MIDR can't be
used to identify its presence, and reading an SoC-specific revision
register from common arch timer code would be awkward.  So, describe it
in the device tree.

Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
 Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index ad440a2..e926aea 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -31,6 +31,12 @@ to deliver its interrupts via SPIs.
   This also affects writes to the tval register, due to the implicit
   counter read.
 
+- hisilicon,erratum-161010101 : A boolean property. Indicates the
+  presence of Hisilicon erratum 161010101, which says that reading the
+  counters is unreliable in some cases, and reads may return a value 32
+  beyond the correct value. This also affects writes to the tval
+  registers, due to the implicit counter read.
+
 ** Optional properties:
 
 - arm,cpu-registers-not-fw-configured : Firmware does not initialize
-- 
1.9.1

[PATCH 3/7] arm64: arm_arch_timer: remove fsl-a008585 parameter

[Mark Rutland]

From: Ding Tianhong <dingtianhong@huawei.com>

Having a command line option to flip the errata handling for a
particular erratum is a little bit unusual, and it's vastly superior to
pass this in the DT. By common consensus, it's best to kill off the
command line parameter.

Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
[Mark: split patch, reword commit message]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
 Documentation/admin-guide/kernel-parameters.txt |  9 ---------
 drivers/clocksource/arm_arch_timer.c            | 14 --------------
 2 files changed, 23 deletions(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index be7c0d9..d8fc55a 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -549,15 +549,6 @@
 			loops can be debugged more effectively on production
 			systems.
 
-	clocksource.arm_arch_timer.fsl-a008585=
-			[ARM64]
-			Format: <bool>
-			Enable/disable the workaround of Freescale/NXP
-			erratum A-008585.  This can be useful for KVM
-			guests, if the guest device tree doesn't show the
-			erratum.  If unspecified, the workaround is
-			enabled based on the device tree.
-
 	clearcpuid=BITNUM [X86]
 			Disable CPUID feature X for the kernel. See
 			arch/x86/include/asm/cpufeatures.h for the valid bit
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 4c8c3fb..6a9d031 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -101,20 +101,6 @@ static int __init early_evtstrm_cfg(char *buf)
 
 static int fsl_a008585_enable = -1;
 
-static int __init early_fsl_a008585_cfg(char *buf)
-{
-	int ret;
-	bool val;
-
-	ret = strtobool(buf, &val);
-	if (ret)
-		return ret;
-
-	fsl_a008585_enable = val;
-	return 0;
-}
-early_param("clocksource.arm_arch_timer.fsl-a008585", early_fsl_a008585_cfg);
-
 u32 __fsl_a008585_read_cntp_tval_el0(void)
 {
 	return __fsl_a008585_read_reg(cntp_tval_el0);
-- 
1.9.1

[PATCH 4/7] arm64: arch_timer: introduce generic errata handling infrastructure

[Mark Rutland]

From: Ding Tianhong <dingtianhong@huawei.com>

Currently we have code inline in the arch timer probe path to cater for
Freescale erratum A-008585, complete with ifdeffery. This is a little
ugly, and will get worse as we try to add more errata handling.

This patch refactors the handling of Freescale erratum A-008585. Now the
erratum is described in a generic arch_timer_erratum_workaround
structure, and the probe path can iterate over these to detect errata
and enable workarounds.

This will simplify the addition and maintenance of code handling
Hisilicon erratum 161010101.

Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
[Mark: split patch, correct Kconfig, reword commit message]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
 arch/arm64/include/asm/arch_timer.h  | 38 +++++----------
 drivers/clocksource/Kconfig          |  4 ++
 drivers/clocksource/arm_arch_timer.c | 92 ++++++++++++++++++++++++------------
 3 files changed, 80 insertions(+), 54 deletions(-)

diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index eaa5bbe..b4b3400 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -29,41 +29,29 @@
 
 #include <clocksource/arm_arch_timer.h>
 
-#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585)
+#if IS_ENABLED(CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND)
 extern struct static_key_false arch_timer_read_ool_enabled;
-#define needs_fsl_a008585_workaround() \
+#define needs_unstable_timer_counter_workaround() \
 	static_branch_unlikely(&arch_timer_read_ool_enabled)
 #else
-#define needs_fsl_a008585_workaround()  false
+#define needs_unstable_timer_counter_workaround()  false
 #endif
 
-u32 __fsl_a008585_read_cntp_tval_el0(void);
-u32 __fsl_a008585_read_cntv_tval_el0(void);
-u64 __fsl_a008585_read_cntvct_el0(void);
 
-/*
- * The number of retries is an arbitrary value well beyond the highest number
- * of iterations the loop has been observed to take.
- */
-#define __fsl_a008585_read_reg(reg) ({			\
-	u64 _old, _new;					\
-	int _retries = 200;				\
-							\
-	do {						\
-		_old = read_sysreg(reg);		\
-		_new = read_sysreg(reg);		\
-		_retries--;				\
-	} while (unlikely(_old != _new) && _retries);	\
-							\
-	WARN_ON_ONCE(!_retries);			\
-	_new;						\
-})
+struct arch_timer_erratum_workaround {
+	const char *id;		/* Indicate the Erratum ID */
+	u32 (*read_cntp_tval_el0)(void);
+	u32 (*read_cntv_tval_el0)(void);
+	u64 (*read_cntvct_el0)(void);
+};
+
+extern const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround;
 
 #define arch_timer_reg_read_stable(reg) 		\
 ({							\
 	u64 _val;					\
-	if (needs_fsl_a008585_workaround())		\
-		_val = __fsl_a008585_read_##reg();	\
+	if (needs_unstable_timer_counter_workaround())		\
+		_val = timer_unstable_counter_workaround->read_##reg();\
 	else						\
 		_val = read_sysreg(reg);		\
 	_val;						\
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 4866f7a..e132bb3 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -325,10 +325,14 @@ config ARM_ARCH_TIMER_EVTSTREAM
 	  This must be disabled for hardware validation purposes to detect any
 	  hardware anomalies of missing events.
 
+config ARM_ARCH_TIMER_OOL_WORKAROUND
+	bool
+
 config FSL_ERRATUM_A008585
 	bool "Workaround for Freescale/NXP Erratum A-008585"
 	default y
 	depends on ARM_ARCH_TIMER && ARM64
+	select ARM_ARCH_TIMER_OOL_WORKAROUND
 	help
 	  This option enables a workaround for Freescale/NXP Erratum
 	  A-008585 ("ARM generic timer may contain an erroneous
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 6a9d031..2af0739 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -96,27 +96,58 @@ static int __init early_evtstrm_cfg(char *buf)
  */
 
 #ifdef CONFIG_FSL_ERRATUM_A008585
-DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
-EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
-
-static int fsl_a008585_enable = -1;
-
-u32 __fsl_a008585_read_cntp_tval_el0(void)
+/*
+ * The number of retries is an arbitrary value well beyond the highest number
+ * of iterations the loop has been observed to take.
+ */
+#define __fsl_a008585_read_reg(reg) ({			\
+	u64 _old, _new;					\
+	int _retries = 200;				\
+							\
+	do {						\
+		_old = read_sysreg(reg);		\
+		_new = read_sysreg(reg);		\
+		_retries--;				\
+	} while (unlikely(_old != _new) && _retries);	\
+							\
+	WARN_ON_ONCE(!_retries);			\
+	_new;						\
+})
+
+static u32 notrace fsl_a008585_read_cntp_tval_el0(void)
 {
 	return __fsl_a008585_read_reg(cntp_tval_el0);
 }
 
-u32 __fsl_a008585_read_cntv_tval_el0(void)
+static u32 notrace fsl_a008585_read_cntv_tval_el0(void)
 {
 	return __fsl_a008585_read_reg(cntv_tval_el0);
 }
 
-u64 __fsl_a008585_read_cntvct_el0(void)
+static u64 notrace fsl_a008585_read_cntvct_el0(void)
 {
 	return __fsl_a008585_read_reg(cntvct_el0);
 }
-EXPORT_SYMBOL(__fsl_a008585_read_cntvct_el0);
-#endif /* CONFIG_FSL_ERRATUM_A008585 */
+#endif
+
+#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
+const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL;
+EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
+
+DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
+EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
+
+static const struct arch_timer_erratum_workaround ool_workarounds[] = {
+#ifdef CONFIG_FSL_ERRATUM_A008585
+	{
+		.id = "fsl,erratum-a008585",
+		.read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
+		.read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
+		.read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
+	},
+#endif
+};
+#endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
 
 static __always_inline
 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
@@ -267,8 +298,8 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
 	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 }
 
-#ifdef CONFIG_FSL_ERRATUM_A008585
-static __always_inline void fsl_a008585_set_next_event(const int access,
+#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
+static __always_inline void erratum_set_next_event_generic(const int access,
 		unsigned long evt, struct clock_event_device *clk)
 {
 	unsigned long ctrl;
@@ -286,20 +317,20 @@ static __always_inline void fsl_a008585_set_next_event(const int access,
 	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 }
 
-static int fsl_a008585_set_next_event_virt(unsigned long evt,
+static int erratum_set_next_event_virt(unsigned long evt,
 					   struct clock_event_device *clk)
 {
-	fsl_a008585_set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
+	erratum_set_next_event_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
 	return 0;
 }
 
-static int fsl_a008585_set_next_event_phys(unsigned long evt,
+static int erratum_set_next_event_phys(unsigned long evt,
 					   struct clock_event_device *clk)
 {
-	fsl_a008585_set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
+	erratum_set_next_event_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
 	return 0;
 }
-#endif /* CONFIG_FSL_ERRATUM_A008585 */
+#endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
 
 static int arch_timer_set_next_event_virt(unsigned long evt,
 					  struct clock_event_device *clk)
@@ -329,16 +360,16 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
 	return 0;
 }
 
-static void fsl_a008585_set_sne(struct clock_event_device *clk)
+static void erratum_workaround_set_sne(struct clock_event_device *clk)
 {
-#ifdef CONFIG_FSL_ERRATUM_A008585
+#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
 	if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
 		return;
 
 	if (arch_timer_uses_ppi == VIRT_PPI)
-		clk->set_next_event = fsl_a008585_set_next_event_virt;
+		clk->set_next_event = erratum_set_next_event_virt;
 	else
-		clk->set_next_event = fsl_a008585_set_next_event_phys;
+		clk->set_next_event = erratum_set_next_event_phys;
 #endif
 }
 
@@ -371,7 +402,7 @@ static void __arch_timer_setup(unsigned type,
 			BUG();
 		}
 
-		fsl_a008585_set_sne(clk);
+		erratum_workaround_set_sne(clk);
 	} else {
 		clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
 		clk->name = "arch_mem_timer";
@@ -591,7 +622,7 @@ static void __init arch_counter_register(unsigned type)
 
 		clocksource_counter.archdata.vdso_direct = true;
 
-#ifdef CONFIG_FSL_ERRATUM_A008585
+#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
 		/*
 		 * Don't use the vdso fastpath if errata require using
 		 * the out-of-line counter accessor.
@@ -879,12 +910,15 @@ static int __init arch_timer_of_init(struct device_node *np)
 
 	arch_timer_c3stop = !of_property_read_bool(np, "always-on");
 
-#ifdef CONFIG_FSL_ERRATUM_A008585
-	if (fsl_a008585_enable < 0)
-		fsl_a008585_enable = of_property_read_bool(np, "fsl,erratum-a008585");
-	if (fsl_a008585_enable) {
-		static_branch_enable(&arch_timer_read_ool_enabled);
-		pr_info("Enabling workaround for FSL erratum A-008585\n");
+#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
+	for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
+		if (of_property_read_bool(np, ool_workarounds[i].id)) {
+			timer_unstable_counter_workaround = &ool_workarounds[i];
+			static_branch_enable(&arch_timer_read_ool_enabled);
+			pr_info("arch_timer: Enabling workaround for %s\n",
+				timer_unstable_counter_workaround->id);
+			break;
+		}
 	}
 #endif
 
-- 
1.9.1

[PATCH 5/7] arm64: arch_timer: work around Hisilicon erratum 161010101

[Mark Rutland]

From: Ding Tianhong <dingtianhong@huawei.com>

Erratum Hisilicon-161010101 says that the ARM generic timer counter "has
the potential to contain an erroneous value when the timer value
changes". Accesses to TVAL (both read and write) are also affected due
to the implicit counter read. Accesses to CVAL are not affected.

The workaround is to reread the system count registers until the value
of the second read is larger than the first one by less than 32, the
system counter can be guaranteed not to return wrong value twice by
back-to-back read and the error value is always larger than the correct
one by 32. Writes to TVAL are replaced with an equivalent write to CVAL.

Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
[Mark: split patch, fix Kconfig, reword commit message]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
 drivers/clocksource/Kconfig          | 10 ++++++++
 drivers/clocksource/arm_arch_timer.c | 49 ++++++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+)

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index e132bb3..17ee71c 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -339,6 +339,16 @@ config FSL_ERRATUM_A008585
 	  value").  The workaround will only be active if the
 	  fsl,erratum-a008585 property is found in the timer node.
 
+config HISILICON_ERRATUM_161010101
+	bool "Workaround for Hisilicon Erratum 161010101"
+	default y
+	select ARM_ARCH_TIMER_OOL_WORKAROUND
+	depends on ARM_ARCH_TIMER && ARM64
+	help
+	  This option enables a workaround for Hisilicon Erratum
+	  161010101. The workaround will be active if the hisilicon,erratum-161010101
+	  property is found in the timer node.
+
 config ARM_GLOBAL_TIMER
 	bool "Support for the ARM global timer" if COMPILE_TEST
 	select CLKSRC_OF if OF
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 2af0739..7b06aef 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -130,6 +130,47 @@ static u64 notrace fsl_a008585_read_cntvct_el0(void)
 }
 #endif
 
+#ifdef CONFIG_HISILICON_ERRATUM_161010101
+/*
+ * Verify whether the value of the second read is larger than the first by
+ * less than 32 is the only way to confirm the value is correct, so clear the
+ * lower 5 bits to check whether the difference is greater than 32 or not.
+ * Theoretically the erratum should not occur more than twice in succession
+ * when reading the system counter, but it is possible that some interrupts
+ * may lead to more than twice read errors, triggering the warning, so setting
+ * the number of retries far beyond the number of iterations the loop has been
+ * observed to take.
+ */
+#define __hisi_161010101_read_reg(reg) ({				\
+	u64 _old, _new;						\
+	int _retries = 50;					\
+								\
+	do {							\
+		_old = read_sysreg(reg);			\
+		_new = read_sysreg(reg);			\
+		_retries--;					\
+	} while (unlikely((_new - _old) >> 5) && _retries);	\
+								\
+	WARN_ON_ONCE(!_retries);				\
+	_new;							\
+})
+
+static u32 notrace hisi_161010101_read_cntp_tval_el0(void)
+{
+	return __hisi_161010101_read_reg(cntp_tval_el0);
+}
+
+static u32 notrace hisi_161010101_read_cntv_tval_el0(void)
+{
+	return __hisi_161010101_read_reg(cntv_tval_el0);
+}
+
+static u64 notrace hisi_161010101_read_cntvct_el0(void)
+{
+	return __hisi_161010101_read_reg(cntvct_el0);
+}
+#endif
+
 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
 const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL;
 EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
@@ -146,6 +187,14 @@ static u64 notrace fsl_a008585_read_cntvct_el0(void)
 		.read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
 	},
 #endif
+#ifdef CONFIG_HISILICON_ERRATUM_161010101
+	{
+		.id = "hisilicon,erratum-161010101",
+		.read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
+		.read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
+		.read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
+	},
+#endif
 };
 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
 
-- 
1.9.1

[PATCH 6/7] arm64: arch_timer: document Hisilicon erratum 161010101

[Mark Rutland]

From: Ding Tianhong <dingtianhong@huawei.com>

Now that we have a workaround for Hisilicon erratum 161010101, notes
this in the arm64 silicon-errata document.

The new config option is too long to fit in the existing kconfig column,
so this is widened to accomodate it.

Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
[Mark: split patch, reword commit message]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
 Documentation/arm64/silicon-errata.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 4a5e6cc..e12c926 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -63,3 +63,5 @@ stable kernels.
 | Cavium         | ThunderX SMMUv2 | #27704          | N/A                              |
 |                |                 |                 |                                  |
 | Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585              |
+|                |                 |                 |                                  |
+| Hisilicon      | Hip0{5,6,7}     | #161010101      | HISILICON_ERRATUM_161010101      |
-- 
1.9.1

[PATCH 7/7] arm64: arch timer: Add timer erratum property for Hip05-d02 and Hip06-d03

[Mark Rutland]

From: Ding Tianhong <dingtianhong@huawei.com>

Enable workaround for hisilicon erratum 161010101 on Hip05-d02 and
Hip06-d03 board.

Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
 arch/arm64/boot/dts/hisilicon/hip05.dtsi | 1 +
 arch/arm64/boot/dts/hisilicon/hip06.dtsi | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index 4b472a3..6b76f3a 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -281,6 +281,7 @@
 			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+		hisilicon,erratum-161010101;
 	};
 
 	pmu {
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index a049b64..cf8b9db 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -260,6 +260,7 @@
 			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+		hisilicon,erratum-161010101;
 	};
 
 	pmu {
-- 
1.9.1

Re: [PATCH 6/7] arm64: arch_timer: document Hisilicon erratum 161010101

[Will Deacon]

On Tue, Jan 31, 2017 at 12:19:55PM +0000, Mark Rutland wrote:
> From: Ding Tianhong <dingtianhong@huawei.com>
> 
> Now that we have a workaround for Hisilicon erratum 161010101, notes
> this in the arm64 silicon-errata document.
> 
> The new config option is too long to fit in the existing kconfig column,
> so this is widened to accomodate it.
> 
> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
> [Mark: split patch, reword commit message]
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> ---
>  Documentation/arm64/silicon-errata.txt | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
> index 4a5e6cc..e12c926 100644
> --- a/Documentation/arm64/silicon-errata.txt
> +++ b/Documentation/arm64/silicon-errata.txt
> @@ -63,3 +63,5 @@ stable kernels.
>  | Cavium         | ThunderX SMMUv2 | #27704          | N/A                              |
>  |                |                 |                 |                                  |
>  | Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585              |
> +|                |                 |                 |                                  |
> +| Hisilicon      | Hip0{5,6,7}     | #161010101      | HISILICON_ERRATUM_161010101      |
> -- 
> 1.9.1

I'd like to take this one via arm64, then you can drop it along with the
first patch in the series and I can deal with the conflicts in the text
file.

Daniel, are you ok with that? This file isn't part of the clocksource
code and is purely an informative document that we maintain to help ARM
vendors know which errata we're working around.

Will

Re: [PATCH 3/7] arm64: arm_arch_timer: remove fsl-a008585 parameter

[Daniel Lezcano]

On Tue, Jan 31, 2017 at 12:19:52PM +0000, Mark Rutland wrote:
> From: Ding Tianhong <dingtianhong@huawei.com>
> 
> Having a command line option to flip the errata handling for a
> particular erratum is a little bit unusual, and it's vastly superior to
> pass this in the DT. By common consensus, it's best to kill off the
> command line parameter.
> 
> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
> [Mark: split patch, reword commit message]
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> ---

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>

-- 

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Re: [PATCH 4/7] arm64: arch_timer: introduce generic errata handling infrastructure

[Daniel Lezcano]

On Tue, Jan 31, 2017 at 12:19:53PM +0000, Mark Rutland wrote:
> From: Ding Tianhong <dingtianhong@huawei.com>
> 
> Currently we have code inline in the arch timer probe path to cater for
> Freescale erratum A-008585, complete with ifdeffery. This is a little
> ugly, and will get worse as we try to add more errata handling.
> 
> This patch refactors the handling of Freescale erratum A-008585. Now the
> erratum is described in a generic arch_timer_erratum_workaround
> structure, and the probe path can iterate over these to detect errata
> and enable workarounds.
> 
> This will simplify the addition and maintenance of code handling
> Hisilicon erratum 161010101.
> 
> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
> [Mark: split patch, correct Kconfig, reword commit message]
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Re: [PATCH 4/7] arm64: arch_timer: introduce generic errata handling infrastructure

[Daniel Lezcano]

On Tue, Jan 31, 2017 at 12:19:53PM +0000, Mark Rutland wrote:
> From: Ding Tianhong <dingtianhong@huawei.com>
> 
> Currently we have code inline in the arch timer probe path to cater for
> Freescale erratum A-008585, complete with ifdeffery. This is a little
> ugly, and will get worse as we try to add more errata handling.
> 
> This patch refactors the handling of Freescale erratum A-008585. Now the
> erratum is described in a generic arch_timer_erratum_workaround
> structure, and the probe path can iterate over these to detect errata
> and enable workarounds.
> 
> This will simplify the addition and maintenance of code handling
> Hisilicon erratum 161010101.
> 
> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
> [Mark: split patch, correct Kconfig, reword commit message]
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> ---

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Re: [PATCH 5/7] arm64: arch_timer: work around Hisilicon erratum 161010101

[Mark Rutland]

Hi Daniel,

On Tue, Jan 31, 2017 at 12:19:54PM +0000, Mark Rutland wrote:
> From: Ding Tianhong <dingtianhong@huawei.com>
> 
> Erratum Hisilicon-161010101 says that the ARM generic timer counter "has
> the potential to contain an erroneous value when the timer value
> changes". Accesses to TVAL (both read and write) are also affected due
> to the implicit counter read. Accesses to CVAL are not affected.
> 
> The workaround is to reread the system count registers until the value
> of the second read is larger than the first one by less than 32, the
> system counter can be guaranteed not to return wrong value twice by
> back-to-back read and the error value is always larger than the correct
> one by 32. Writes to TVAL are replaced with an equivalent write to CVAL.
> 
> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
> [Mark: split patch, fix Kconfig, reword commit message]
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> ---
>  drivers/clocksource/Kconfig          | 10 ++++++++
>  drivers/clocksource/arm_arch_timer.c | 49 ++++++++++++++++++++++++++++++++++++
>  2 files changed, 59 insertions(+)

Do you have any comments on this patch?

What would you prefer to do w.r.t. taking these patches? Would you like
me to resend the clocksource patches in isolation, or as a pull?

Thanks,
Mark.

> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index e132bb3..17ee71c 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -339,6 +339,16 @@ config FSL_ERRATUM_A008585
>  	  value").  The workaround will only be active if the
>  	  fsl,erratum-a008585 property is found in the timer node.
>  
> +config HISILICON_ERRATUM_161010101
> +	bool "Workaround for Hisilicon Erratum 161010101"
> +	default y
> +	select ARM_ARCH_TIMER_OOL_WORKAROUND
> +	depends on ARM_ARCH_TIMER && ARM64
> +	help
> +	  This option enables a workaround for Hisilicon Erratum
> +	  161010101. The workaround will be active if the hisilicon,erratum-161010101
> +	  property is found in the timer node.
> +
>  config ARM_GLOBAL_TIMER
>  	bool "Support for the ARM global timer" if COMPILE_TEST
>  	select CLKSRC_OF if OF
> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
> index 2af0739..7b06aef 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -130,6 +130,47 @@ static u64 notrace fsl_a008585_read_cntvct_el0(void)
>  }
>  #endif
>  
> +#ifdef CONFIG_HISILICON_ERRATUM_161010101
> +/*
> + * Verify whether the value of the second read is larger than the first by
> + * less than 32 is the only way to confirm the value is correct, so clear the
> + * lower 5 bits to check whether the difference is greater than 32 or not.
> + * Theoretically the erratum should not occur more than twice in succession
> + * when reading the system counter, but it is possible that some interrupts
> + * may lead to more than twice read errors, triggering the warning, so setting
> + * the number of retries far beyond the number of iterations the loop has been
> + * observed to take.
> + */
> +#define __hisi_161010101_read_reg(reg) ({				\
> +	u64 _old, _new;						\
> +	int _retries = 50;					\
> +								\
> +	do {							\
> +		_old = read_sysreg(reg);			\
> +		_new = read_sysreg(reg);			\
> +		_retries--;					\
> +	} while (unlikely((_new - _old) >> 5) && _retries);	\
> +								\
> +	WARN_ON_ONCE(!_retries);				\
> +	_new;							\
> +})
> +
> +static u32 notrace hisi_161010101_read_cntp_tval_el0(void)
> +{
> +	return __hisi_161010101_read_reg(cntp_tval_el0);
> +}
> +
> +static u32 notrace hisi_161010101_read_cntv_tval_el0(void)
> +{
> +	return __hisi_161010101_read_reg(cntv_tval_el0);
> +}
> +
> +static u64 notrace hisi_161010101_read_cntvct_el0(void)
> +{
> +	return __hisi_161010101_read_reg(cntvct_el0);
> +}
> +#endif
> +
>  #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
>  const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL;
>  EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
> @@ -146,6 +187,14 @@ static u64 notrace fsl_a008585_read_cntvct_el0(void)
>  		.read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
>  	},
>  #endif
> +#ifdef CONFIG_HISILICON_ERRATUM_161010101
> +	{
> +		.id = "hisilicon,erratum-161010101",
> +		.read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
> +		.read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
> +		.read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
> +	},
> +#endif
>  };
>  #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
>  
> -- 
> 1.9.1
> 

Re: [PATCH 5/7] arm64: arch_timer: work around Hisilicon erratum 161010101

[Daniel Lezcano]

On Tue, Jan 31, 2017 at 12:19:54PM +0000, Mark Rutland wrote:
> From: Ding Tianhong <dingtianhong@huawei.com>
> 
> Erratum Hisilicon-161010101 says that the ARM generic timer counter "has
> the potential to contain an erroneous value when the timer value
> changes". Accesses to TVAL (both read and write) are also affected due
> to the implicit counter read. Accesses to CVAL are not affected.
> 
> The workaround is to reread the system count registers until the value
> of the second read is larger than the first one by less than 32, the
> system counter can be guaranteed not to return wrong value twice by
> back-to-back read and the error value is always larger than the correct
> one by 32. Writes to TVAL are replaced with an equivalent write to CVAL.
> 
> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
> [Mark: split patch, fix Kconfig, reword commit message]
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> ---

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>