From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753271AbdBFNkZ (ORCPT ); Mon, 6 Feb 2017 08:40:25 -0500 Received: from mail-wj0-f196.google.com ([209.85.210.196]:35329 "EHLO mail-wj0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753193AbdBFNkV (ORCPT ); Mon, 6 Feb 2017 08:40:21 -0500 From: Jan Glauber To: Ulf Hansson Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, David Daney , "Steven J . Hill" , Jan Glauber , David Daney , "Steven J . Hill" Subject: [PATCH v11 8/9] mmc: cavium: Support DDR mode for eMMC devices Date: Mon, 6 Feb 2017 14:39:51 +0100 Message-Id: <20170206133953.8390-9-jglauber@cavium.com> X-Mailer: git-send-email 2.9.0.rc0.21.g7777322 In-Reply-To: <20170206133953.8390-1-jglauber@cavium.com> References: <20170206133953.8390-1-jglauber@cavium.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for switching to DDR mode for eMMC devices. Although the host controller only supports 3.3 Volt and DDR52 uses 1.8 Volt according to the specification it is possible to use DDR also with 3.3 Volt for eMMC chips. To switch to DDR mode MMC_CAP_1_8V_DDR is required. Signed-off-by: Jan Glauber Signed-off-by: David Daney Signed-off-by: Steven J. Hill --- drivers/mmc/host/cavium-mmc.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/cavium-mmc.c b/drivers/mmc/host/cavium-mmc.c index 3d3c9c7..8fcb82a 100644 --- a/drivers/mmc/host/cavium-mmc.c +++ b/drivers/mmc/host/cavium-mmc.c @@ -858,6 +858,10 @@ static void cvm_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) break; } + /* DDR is available for 4/8 bit bus width */ + if (ios->bus_width && ios->timing == MMC_TIMING_MMC_DDR52) + bus_width |= 4; + slot->bus_width = bus_width; if (!ios->clock) @@ -1091,8 +1095,14 @@ int cvm_mmc_slot_probe(struct device *dev, struct cvm_mmc_host *host) /* Set up host parameters */ mmc->ops = &cvm_mmc_ops; + /* + * We only have a 3.3v supply, we cannot support any + * of the UHS modes. We do support the high speed DDR + * modes up to 52MHz. + */ mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | - MMC_CAP_ERASE | MMC_CAP_CMD23 | MMC_CAP_POWER_OFF_CARD; + MMC_CAP_ERASE | MMC_CAP_CMD23 | MMC_CAP_POWER_OFF_CARD | + MMC_CAP_3_3V_DDR; if (host->use_sg) mmc->max_segs = 16; -- 2.9.0.rc0.21.g7777322