From: Kyle Huey <me@kylehuey.com>
To: "Robert O'Callahan" <robert@ocallahan.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Andy Lutomirski" <luto@kernel.org>,
"Ingo Molnar" <mingo@redhat.com>,
"H. Peter Anvin" <hpa@zytor.com>,
x86@kernel.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"Radim Krčmář" <rkrcmar@redhat.com>,
"Jeff Dike" <jdike@addtoit.com>,
"Richard Weinberger" <richard@nod.at>,
"Alexander Viro" <viro@zeniv.linux.org.uk>,
"Shuah Khan" <shuah@kernel.org>,
"Dave Hansen" <dave.hansen@linux.intel.com>,
"Borislav Petkov" <bp@suse.de>,
"Peter Zijlstra" <peterz@infradead.org>,
"Boris Ostrovsky" <boris.ostrovsky@oracle.com>,
"Len Brown" <len.brown@intel.com>,
"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
"Dmitry Safonov" <dsafonov@virtuozzo.com>,
"David Matlack" <dmatlack@google.com>,
"Nadav Amit" <nadav.amit@gmail.com>,
"Andi Kleen" <andi@firstfloor.org>
Cc: linux-kernel@vger.kernel.org,
user-mode-linux-devel@lists.sourceforge.net,
user-mode-linux-user@lists.sourceforge.net,
linux-fsdevel@vger.kernel.org, linux-kselftest@vger.kernel.org,
kvm@vger.kernel.org
Subject: [PATCH v14 5/9] x86/cpufeature: Detect CPUID faulting support
Date: Wed, 8 Feb 2017 00:09:13 -0800 [thread overview]
Message-ID: <20170208080917.24320-6-khuey@kylehuey.com> (raw)
In-Reply-To: <20170208080917.24320-1-khuey@kylehuey.com>
Intel supports faulting on the CPUID instruction beginning with Ivy Bridge.
When enabled, the processor will fault on attempts to execute the CPUID
instruction with CPL>0. This will allow a ptracer to emulate the CPUID
instruction.
Bit 31 of MSR_PLATFORM_INFO advertises support for this feature. It is
documented in detail in Section 2.3.2 of
https://bugzilla.kernel.org/attachment.cgi?id=243991
Detect support for this feature and expose it as X86_FEATURE_CPUID_FAULT.
Signed-off-by: Kyle Huey <khuey@kylehuey.com>
Reviewed-by: Borislav Petkov <bp@suse.de>
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/msr-index.h | 2 ++
arch/x86/kernel/cpu/intel.c | 12 ++++++++++++
3 files changed, 15 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index eafee3161d1c..c70cab24f648 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -182,16 +182,17 @@
/*
* Auxiliary flags: Linux defined - For features scattered in various
* CPUID levels like 0x6, 0xA etc, word 7.
*
* Reuse free bits when adding new feature flags!
*/
+#define X86_FEATURE_CPUID_FAULT ( 7*32+ 0) /* Intel CPUID faulting */
#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */
#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
#define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */
#define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */
#define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */
#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 710273c617b8..8192b3111c84 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -40,16 +40,18 @@
#define MSR_PPIN_CTL 0x0000004e
#define MSR_PPIN 0x0000004f
#define MSR_IA32_PERFCTR0 0x000000c1
#define MSR_IA32_PERFCTR1 0x000000c2
#define MSR_FSB_FREQ 0x000000cd
#define MSR_PLATFORM_INFO 0x000000ce
+#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31
+#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
#define NHM_C3_AUTO_DEMOTE (1UL << 25)
#define NHM_C1_AUTO_DEMOTE (1UL << 26)
#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 203f860d2ab3..3d9e11b2b41a 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -442,16 +442,26 @@ static void intel_bsp_resume(struct cpuinfo_x86 *c)
{
/*
* MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume,
* so reinitialize it properly like during bootup:
*/
init_intel_energy_perf(c);
}
+static void init_intel_misc_features(struct cpuinfo_x86 *c)
+{
+ u64 msr;
+
+ if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
+ if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
+ set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
+ }
+}
+
static void init_intel(struct cpuinfo_x86 *c)
{
unsigned int l2 = 0;
early_init_intel(c);
intel_workarounds(c);
@@ -555,16 +565,18 @@ static void init_intel(struct cpuinfo_x86 *c)
/* Work around errata */
srat_detect_node(c);
if (cpu_has(c, X86_FEATURE_VMX))
detect_vmx_virtcap(c);
init_intel_energy_perf(c);
+
+ init_intel_misc_features(c);
}
#ifdef CONFIG_X86_32
static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
{
/*
* Intel PIII Tualatin. This comes in two flavours.
* One has 256kb of cache, the other 512. We have no way
--
2.11.0
next prev parent reply other threads:[~2017-02-08 8:11 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-08 8:09 [PATCH v14 0/9] x86/arch_prctl Add ARCH_[GET|SET]_CPUID for controlling the CPUID instruction Kyle Huey
2017-02-08 8:09 ` [PATCH v14 1/9] x86/arch_prctl/64: Use SYSCALL_DEFINE2 to define sys_arch_prctl Kyle Huey
2017-02-08 8:09 ` [PATCH v14 2/9] x86/arch_prctl/64: Rename do_arch_prctl to do_arch_prctl_64 Kyle Huey
2017-02-08 8:09 ` [PATCH v14 3/9] x86/arch_prctl: Add do_arch_prctl_common Kyle Huey
2017-02-08 8:09 ` [PATCH v14 4/9] x86/syscalls/32: Wire up arch_prctl on x86-32 Kyle Huey
2017-02-08 8:09 ` Kyle Huey [this message]
2017-02-08 8:09 ` [PATCH v14 6/9] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID Kyle Huey
2017-02-08 8:09 ` [PATCH v14 7/9] x86/arch_prctl: Selftest for ARCH_[GET|SET]_CPUID Kyle Huey
2017-02-08 8:09 ` [PATCH v14 8/9] KVM: x86: virtualize cpuid faulting Kyle Huey
2018-07-27 17:15 ` Jim Mattson
2018-07-27 19:41 ` Andy Lutomirski
2018-07-27 20:28 ` Jim Mattson
2018-07-27 20:46 ` Andy Lutomirski
2018-07-27 21:03 ` Jim Mattson
2018-07-27 21:05 ` Andy Lutomirski
2018-07-27 21:30 ` Jim Mattson
2018-07-27 22:58 ` Andy Lutomirski
2017-02-08 8:09 ` [PATCH v14 9/9] x86/arch_prctl: Rename 'code' argument to 'option' Kyle Huey
2017-02-10 13:07 ` [PATCH v14 0/9] x86/arch_prctl Add ARCH_[GET|SET]_CPUID for controlling the CPUID instruction Thomas Gleixner
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