From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752100AbdBIJUt convert rfc822-to-8bit (ORCPT ); Thu, 9 Feb 2017 04:20:49 -0500 Received: from tyo162.gate.nec.co.jp ([114.179.232.162]:43865 "EHLO tyo162.gate.nec.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751946AbdBIJUp (ORCPT ); Thu, 9 Feb 2017 04:20:45 -0500 From: Naoya Horiguchi To: Zi Yan CC: "linux-kernel@vger.kernel.org" , "linux-mm@kvack.org" , "kirill.shutemov@linux.intel.com" , "akpm@linux-foundation.org" , "minchan@kernel.org" , "vbabka@suse.cz" , "mgorman@techsingularity.net" , "khandual@linux.vnet.ibm.com" , "zi.yan@cs.rutgers.edu" Subject: Re: [PATCH v3 04/14] mm: x86: move _PAGE_SWP_SOFT_DIRTY from bit 7 to bit 1 Thread-Topic: [PATCH v3 04/14] mm: x86: move _PAGE_SWP_SOFT_DIRTY from bit 7 to bit 1 Thread-Index: AQHSf8r2d60z4ImNC02zenzXjDcjgqFf04IA Date: Thu, 9 Feb 2017 09:14:58 +0000 Message-ID: <20170209091458.GA15649@hori1.linux.bs1.fc.nec.co.jp> References: <20170205161252.85004-1-zi.yan@sent.com> <20170205161252.85004-5-zi.yan@sent.com> In-Reply-To: <20170205161252.85004-5-zi.yan@sent.com> Accept-Language: en-US, ja-JP Content-Language: ja-JP X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.128.101.7] Content-Type: text/plain; charset="iso-2022-jp" Content-ID: <8DAD67A605EFFB4BB1984EC46D6D79BC@gisp.nec.co.jp> Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Feb 05, 2017 at 11:12:42AM -0500, Zi Yan wrote: > From: Naoya Horiguchi > > pmd_present() checks _PAGE_PSE along with _PAGE_PRESENT to avoid > false negative return when it races with thp spilt > (during which _PAGE_PRESENT is temporary cleared.) I don't think that > dropping _PAGE_PSE check in pmd_present() works well because it can > hurt optimization of tlb handling in thp split. > In the current kernel, bits 1-4 are not used in non-present format > since commit 00839ee3b299 ("x86/mm: Move swap offset/type up in PTE to > work around erratum"). So let's move _PAGE_SWP_SOFT_DIRTY to bit 1. > Bit 7 is used as reserved (always clear), so please don't use it for > other purpose. > > Signed-off-by: Naoya Horiguchi > > ChangeLog v3: > - Move _PAGE_SWP_SOFT_DIRTY to bit 1, it was placed at bit 6. Because > some CPUs might accidentally set bit 5 or 6. > > Signed-off-by: Zi Yan > --- More documenting will be helpful, could you do like follows? Thanks, Naoya Horiguchi --- From: Naoya Horiguchi Date: Sun, 5 Feb 2017 11:12:42 -0500 Subject: [PATCH] mm: x86: move _PAGE_SWP_SOFT_DIRTY from bit 7 to bit 1 pmd_present() checks _PAGE_PSE along with _PAGE_PRESENT to avoid false negative return when it races with thp spilt (during which _PAGE_PRESENT is temporary cleared.) I don't think that dropping _PAGE_PSE check in pmd_present() works well because it can hurt optimization of tlb handling in thp split. In the current kernel, bits 1-4 are not used in non-present format since commit 00839ee3b299 ("x86/mm: Move swap offset/type up in PTE to work around erratum"). So let's move _PAGE_SWP_SOFT_DIRTY to bit 1. Bit 7 is used as reserved (always clear), so please don't use it for other purpose. Signed-off-by: Naoya Horiguchi Signed-off-by: Zi Yan --- arch/x86/include/asm/pgtable_64.h | 12 +++++++++--- arch/x86/include/asm/pgtable_types.h | 10 +++++----- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h index 73c7ccc38912..07c98c85cc96 100644 --- a/arch/x86/include/asm/pgtable_64.h +++ b/arch/x86/include/asm/pgtable_64.h @@ -157,15 +157,21 @@ static inline int pgd_large(pgd_t pgd) { return 0; } /* * Encode and de-code a swap entry * - * | ... | 11| 10| 9|8|7|6|5| 4| 3|2|1|0| <- bit number - * | ... |SW3|SW2|SW1|G|L|D|A|CD|WT|U|W|P| <- bit names - * | OFFSET (14->63) | TYPE (9-13) |0|X|X|X| X| X|X|X|0| <- swp entry + * | ... | 11| 10| 9|8|7|6|5| 4| 3|2| 1|0| <- bit number + * | ... |SW3|SW2|SW1|G|L|D|A|CD|WT|U| W|P| <- bit names + * | OFFSET (14->63) | TYPE (9-13) |0|0|X|X| X| X|X|SD|0| <- swp entry * * G (8) is aliased and used as a PROT_NONE indicator for * !present ptes. We need to start storing swap entries above * there. We also need to avoid using A and D because of an * erratum where they can be incorrectly set by hardware on * non-present PTEs. + * + * SD (1) in swp entry is used to store soft dirty bit, which helps us + * remember soft dirty over page migration. + * + * Bit 7 in swp entry should be 0 because pmd_present checks not only P, + * but G. */ #define SWP_TYPE_FIRST_BIT (_PAGE_BIT_PROTNONE + 1) #define SWP_TYPE_BITS 5 diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h index 8b4de22d6429..3695abd58ef6 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h @@ -97,15 +97,15 @@ /* * Tracking soft dirty bit when a page goes to a swap is tricky. * We need a bit which can be stored in pte _and_ not conflict - * with swap entry format. On x86 bits 6 and 7 are *not* involved - * into swap entry computation, but bit 6 is used for nonlinear - * file mapping, so we borrow bit 7 for soft dirty tracking. + * with swap entry format. On x86 bits 1-4 are *not* involved + * into swap entry computation, but bit 7 is used for thp migration, + * so we borrow bit 1 for soft dirty tracking. * * Please note that this bit must be treated as swap dirty page - * mark if and only if the PTE has present bit clear! + * mark if and only if the PTE/PMD has present bit clear! */ #ifdef CONFIG_MEM_SOFT_DIRTY -#define _PAGE_SWP_SOFT_DIRTY _PAGE_PSE +#define _PAGE_SWP_SOFT_DIRTY _PAGE_RW #else #define _PAGE_SWP_SOFT_DIRTY (_AT(pteval_t, 0)) #endif -- 2.7.4