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Date: Wed, 22 Feb 2017 11:18:48 -0800
From: Andi Kleen <ak@linux.intel.com>
To: "Liang, Kan" <kan.liang@intel.com>
Cc: Vince Weaver <vincent.weaver@maine.edu>,
        Peter Zijlstra <peterz@infradead.org>,
        "Odzioba, Lukasz" <lukasz.odzioba@intel.com>,
        Stephane Eranian <eranian@google.com>,
        "mingo@redhat.com" <mingo@redhat.com>,
        LKML <linux-kernel@vger.kernel.org>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>
Subject: Re: [PATCH] perf/x86: fix event counter update issue
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> No. It related to the counter width. The number of bits we can use should be
> 1 bit less than the total width. Otherwise, there will be problem.
> For big cores such as haswell, broadwell, skylake, the counter width is 48 bit.
> So we can only use 47 bits.
> For Silvermont and KNL, the counter width is only 32 bit I think. So we can only
> use 31 bits.

It is 40 bits on these cores, so 39bits.

-Andi