From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933181AbdCKAc6 (ORCPT ); Fri, 10 Mar 2017 19:32:58 -0500 Received: from mga14.intel.com ([192.55.52.115]:13446 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932912AbdCKAct (ORCPT ); Fri, 10 Mar 2017 19:32:49 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,143,1486454400"; d="scan'208";a="1121140493" From: Andi Kleen To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, Andi Kleen Subject: [PATCH 2/2] x86/fpu: Support disabling AVX and AVX512 Date: Fri, 10 Mar 2017 16:32:41 -0800 Message-Id: <20170311003241.13127-2-andi@firstfloor.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170311003241.13127-1-andi@firstfloor.org> References: <20170311003241.13127-1-andi@firstfloor.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andi Kleen For performance testing it is useful to be able to disable AVX and AVX512. User programs check in XGETBV if AVX is supported by the OS. If we don't initialize the XSAVE state for AVX it will appear as if the OS is not supporting AVX. For kernel users we can also clear the internal cpu feature bits. This patch implements disable options for AVX and AVX512 for the XSAVE code. I originally considered a generic argument that would disable any XSAVE feature, but it turns out you need special code to also disable all the CPUID bits, because otherwise kernel code may assume it exists, when it doesn't. MPX already has an own disable flag. Not clear it is useful for the others. So we only do it for AVX/AVX512 for now. Signed-off-by: Andi Kleen --- Documentation/admin-guide/kernel-parameters.txt | 3 ++ arch/x86/kernel/fpu/xstate.c | 61 +++++++++++++++++++++---- 2 files changed, 55 insertions(+), 9 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 2ba45caabada..d9ae4a2c07ab 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -785,6 +785,9 @@ dhash_entries= [KNL] Set number of hash buckets for dentry cache. + disable_avx [X86] Disable support for AVX on Intel CPUs. + disable_avx512 [X86] Disable support for AVX512 on Intel CPUs. + disable_1tb_segments [PPC] Disables the use of 1TB hash page table segments. This causes the kernel to fall back to 256MB segments which diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index c24ac1efb12d..cf75638ec657 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -16,6 +16,20 @@ #include +enum xsave_features { + XSAVE_X87, + XSAVE_SSE, + XSAVE_AVX, + XSAVE_MPX_BOUNDS, + XSAVE_MPX_CSR, + XSAVE_AVX512_OPMASK, + XSAVE_AVX512_HI256, + XSAVE_AVX512_ZMM_HI256, + XSAVE_PT, + XSAVE_PKU, + XSAVE_UNKNOWN +}; + /* * Although we spell it out in here, the Processor Trace * xfeature is completely unused. We use other mechanisms @@ -41,6 +55,8 @@ static const char *xfeature_names[] = */ u64 xfeatures_mask __read_mostly; +u64 xfeatures_disabled __initdata; + static unsigned int xstate_offsets[XFEATURE_MAX] = { [ 0 ... XFEATURE_MAX - 1] = -1}; static unsigned int xstate_sizes[XFEATURE_MAX] = { [ 0 ... XFEATURE_MAX - 1] = -1}; static unsigned int xstate_comp_offsets[sizeof(xfeatures_mask)*8]; @@ -52,6 +68,21 @@ static unsigned int xstate_comp_offsets[sizeof(xfeatures_mask)*8]; */ unsigned int fpu_user_xstate_size; +static void clear_avx512(void) +{ + setup_clear_cpu_cap(X86_FEATURE_AVX512F); + setup_clear_cpu_cap(X86_FEATURE_AVX512IFMA); + setup_clear_cpu_cap(X86_FEATURE_AVX512PF); + setup_clear_cpu_cap(X86_FEATURE_AVX512ER); + setup_clear_cpu_cap(X86_FEATURE_AVX512CD); + setup_clear_cpu_cap(X86_FEATURE_AVX512DQ); + setup_clear_cpu_cap(X86_FEATURE_AVX512BW); + setup_clear_cpu_cap(X86_FEATURE_AVX512VL); + setup_clear_cpu_cap(X86_FEATURE_AVX512VBMI); + setup_clear_cpu_cap(X86_FEATURE_AVX512_4VNNIW); + setup_clear_cpu_cap(X86_FEATURE_AVX512_4FMAPS); +} + /* * Clear all of the X86_FEATURE_* bits that are unavailable * when the CPU has no XSAVE support. @@ -64,17 +95,9 @@ void fpu__xstate_clear_all_cpu_caps(void) setup_clear_cpu_cap(X86_FEATURE_XSAVES); setup_clear_cpu_cap(X86_FEATURE_AVX); setup_clear_cpu_cap(X86_FEATURE_AVX2); - setup_clear_cpu_cap(X86_FEATURE_AVX512F); - setup_clear_cpu_cap(X86_FEATURE_AVX512IFMA); - setup_clear_cpu_cap(X86_FEATURE_AVX512PF); - setup_clear_cpu_cap(X86_FEATURE_AVX512ER); - setup_clear_cpu_cap(X86_FEATURE_AVX512CD); - setup_clear_cpu_cap(X86_FEATURE_AVX512DQ); - setup_clear_cpu_cap(X86_FEATURE_AVX512BW); - setup_clear_cpu_cap(X86_FEATURE_AVX512VL); + clear_avx512(); setup_clear_cpu_cap(X86_FEATURE_MPX); setup_clear_cpu_cap(X86_FEATURE_XGETBV1); - setup_clear_cpu_cap(X86_FEATURE_AVX512VBMI); setup_clear_cpu_cap(X86_FEATURE_PKU); setup_clear_cpu_cap(X86_FEATURE_AVX512_4VNNIW); setup_clear_cpu_cap(X86_FEATURE_AVX512_4FMAPS); @@ -735,6 +758,7 @@ void __init fpu__init_system_xstate(void) goto out_disable; } + xfeatures_mask &= ~xfeatures_disabled; xfeatures_mask &= fpu__get_supported_xfeatures_mask(); /* Enable xstate instructions to be able to continue with initialization: */ @@ -1080,3 +1104,22 @@ int copyin_to_xsaves(const void *kbuf, const void __user *ubuf, return 0; } + +static int __init parse_disable_avx512(char *str) +{ + xfeatures_disabled |= BIT(XSAVE_AVX512_OPMASK) | + BIT(XSAVE_AVX512_HI256) | + BIT(XSAVE_AVX512_ZMM_HI256); + clear_avx512(); + return 0; +} +early_param("disable_avx512", parse_disable_avx512); + +static int __init parse_disable_avx(char *str) +{ + xfeatures_disabled |= BIT(XSAVE_AVX); + setup_clear_cpu_cap(X86_FEATURE_AVX); + setup_clear_cpu_cap(X86_FEATURE_AVX2); + return parse_disable_avx512(NULL); +} +early_param("disable_avx", parse_disable_avx); -- 2.9.3