From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751413AbdCVUKg (ORCPT ); Wed, 22 Mar 2017 16:10:36 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:48844 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751327AbdCVUKX (ORCPT ); Wed, 22 Mar 2017 16:10:23 -0400 Date: Wed, 22 Mar 2017 21:09:23 +0100 From: Maxime Ripard To: Icenowy Zheng Cc: Rob Herring , Chen-Yu Tsai , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-sunxi@googlegroups.com" Subject: Re: [PATCH v2 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs Message-ID: <20170322200923.tcr7yqnfqj2zk2v7@lukather> References: <20170315172808.64011-1-icenowy@aosc.xyz> <20170315172808.64011-2-icenowy@aosc.xyz> <20170321074117.vdfjynauuuv6fivp@lukather> <115431490120542@web34g.yandex.ru> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="xisbm6zwhvbrtxfv" Content-Disposition: inline In-Reply-To: <115431490120542@web34g.yandex.ru> User-Agent: Mutt/1.6.2-neo (2016-08-21) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --xisbm6zwhvbrtxfv Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Mar 22, 2017 at 02:22:22AM +0800, Icenowy Zheng wrote: >=20 >=20 > 21.03.2017, 15:41, "Maxime Ripard" : > > On Thu, Mar 16, 2017 at 01:28:04AM +0800, Icenowy Zheng wrote: > >> =A0Many Allwinner SoCs after A31 have a CCU in PRCM block. > >> > >> =A0Give the ones on H3 and A64 compatible strings. > >> > >> =A0Signed-off-by: Icenowy Zheng > >> =A0--- > >> =A0Changes in v2: > >> =A0- Add iosc for R_CCU's on H3/A64. (A31, A23 and A33 seem to have di= fferent > >> =A0=A0=A0clock for mux 3 of ar100 clk. Investgations are needed for th= em.) > >> > >> =A0=A0Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 18 +++++= ++++++++++++- > >> =A0=A01 file changed, 17 insertions(+), 1 deletion(-) > >> > >> =A0diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt = b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > >> =A0index 68512aa398a9..4a4addff595d 100644 > >> =A0--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > >> =A0+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > >> =A0@@ -7,9 +7,11 @@ Required properties : > >> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0- "allwinner,sun= 8i-a23-ccu" > >> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0- "allwinner,sun= 8i-a33-ccu" > >> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0- "allwinner,sun= 8i-h3-ccu" > >> =A0+ - "allwinner,sun8i-h3-r-ccu" > >> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0- "allwinner,sun= 8i-v3s-ccu" > >> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0- "allwinner,sun= 9i-a80-ccu" > >> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0- "allwinner,sun= 50i-a64-ccu" > >> =A0+ - "allwinner,sun50i-a64-r-ccu" > >> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0- "allwinner,sun= 50i-h5-ccu" > >> > >> =A0=A0- reg: Must contain the registers base address and length > >> =A0@@ -20,7 +22,11 @@ Required properties : > >> =A0=A0- #clock-cells : must contain 1 > >> =A0=A0- #reset-cells : must contain 1 > >> > >> =A0-Example: > >> =A0+For the PRCM CCUs on H3/A64, one more clock is needed: > >> =A0+- "iosc": another frequency oscillator used for CPUS (usually at 3= 2000Hz, > >> =A0+ not the same with losc) > > > > This is called the internal oscillator in the datasheet, it would > > probably make more sense to call it that way in the documentation too. > > > > This oscillator seems to be clocked at 16MHz, so we should represent > > it as such. > > > > And I'm wondering, are you *sure* that it's fed directly from the > > internal oscillator, or goes through the registers in the RTC, with > > the 32 divider and 16 prescaler by default that makes it at roughly > > the same rate (31.25kHz). >=20 > In fact I know nothing about it -- I only represented the code in BSP > clock driver. >=20 > The mux value 3 varies from SoC to SoC. For A64/H5 it's 32000, > for A33 it's 667000 (seems to be directly the internal OSC, as the > user manual says the internal OSC is 600~700kHz; but it's named > cpuosc rather than iosc in A33 BSP clock driver); for A80 it's even > PLL_AUDIO. Where are you getting those info from? As far as I know, the A33 PRCM takes the hosc, losc, pll6 and CPU (internal) oscillator: https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sun= xi/clk-sun8iw5.c#L508 The H3 takes the hosc and losc: https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sun= xi/clk-sun8iw7.c#L379 The A80 takes the hosc and losc: https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sun= xi/clk-sun9iw1.c#L281 The A64 takes the hosc, losc, pll-periph0 and the iosc, which indeed seems to be fed from the internal oscillator with the divider in the RTC: https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/a= rch/arm64/boot/dts/sun50iw1p1-clk.dtsi#L19 https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65-bsp2.0/d= rivers/clk/sunxi/clk-sun50iw1.c#L603 Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --xisbm6zwhvbrtxfv Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIcBAEBCAAGBQJY0tnvAAoJEBx+YmzsjxAgiGMQAKxEgy65BS6wypY1DPwmtGhf HZioe7x0JgtFOyjYlsgfqzraFOzDsAklecT5V+Av1qcM5d103HpA4HeSRvcDMQYY Im8K4qlJv4EeQVOPf4QNSjKFNJC/g2Ck2FYQSe5/L8GXZuEk2yXE/aejbTz4fIlL KvwHBs3gIMQVjnBpomta4w56nNWOZdEe+9O5JLVP2S654ueMZOoHTcjBdlU5hiRv /0jaY8GMvv5zxUFEWyh5tEsXQxs8wzqJ51J5SfeGU4z/8lmuB7cxTR66LoYaz7cM B2QrHTtnGS0xNchsP1y0kvwkmpRVnS1QNSTlmwBvIDiEmHk++VtHiVBD0OaCl4gm aq/ScqvF3vvQL5QfLS1J+kQy9ZlhD65aRyxZoQDaVTH92NChlzJounNUhFXfoIl0 DXjNZleUi0yEoy8QvjqVKCfaDyj8fZkv+4Bw1VJt4UAd2z4St4dCakdDJjUqQdPT pYRGj0all+8uS0Kq3BVx6CkCajlRYibQKponxNpu4D8xVMyqKThZTP+hC3FKIomr GWiKMxhifbs9Y1ZEJ6OlUIjkOeJFlRf+ID8UGIdRW1ZFW/YKMO8ealUlfthsM3bd TEMisttYcA5YNj5sBV9ltYsMvBo2k0t6/Fu6RYKfc1kEJ3Ld5ve30BCrgPRjf+M5 GRfy9LCWxXhXnX+xSMR+ =fkI5 -----END PGP SIGNATURE----- --xisbm6zwhvbrtxfv--