From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935323AbdDFOks (ORCPT ); Thu, 6 Apr 2017 10:40:48 -0400 Received: from mail-wr0-f195.google.com ([209.85.128.195]:34218 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755841AbdDFOki (ORCPT ); Thu, 6 Apr 2017 10:40:38 -0400 Date: Thu, 6 Apr 2017 16:40:34 +0200 From: Thierry Reding To: Paul Cercueil Cc: Linus Walleij , Alexandre Courbot , Rob Herring , Mark Rutland , Ralf Baechle , Boris Brezillon , Bartlomiej Zolnierkiewicz , Maarten ter Huurne , Lars-Peter Clausen , Paul Burton , james.hogan@imgtec.com, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linux-mmc@vger.kernel.org, linux-mtd@lists.infradead.org, linux-pwm@vger.kernel.org, linux-fbdev@vger.kernel.org Subject: Re: [PATCH v4 13/14] pwm: jz4740: Let the pinctrl driver configure the pins Message-ID: <20170406144034.GE8438@ulmo.ba.sec> References: <20170125185207.23902-2-paul@crapouillou.net> <20170402204244.14216-1-paul@crapouillou.net> <20170402204244.14216-14-paul@crapouillou.net> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="brEuL7wsLY8+TuWz" Content-Disposition: inline In-Reply-To: <20170402204244.14216-14-paul@crapouillou.net> User-Agent: Mutt/1.8.0 (2017-02-23) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --brEuL7wsLY8+TuWz Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Apr 02, 2017 at 10:42:43PM +0200, Paul Cercueil wrote: > Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on > the pins being properly configured before the driver probes. >=20 > One inherent problem of this new approach is that the pinctrl framework > does not allow us to configure each pin on demand, when the various PWM > channels are requested or released. For instance, the PWM channels can > be configured from sysfs, which would require all PWM pins to be configur= ed > properly beforehand for the PWM function, eventually causing conflicts > with other platform or board drivers. >=20 > The proper solution here would be to modify the pwm-jz4740 driver to > handle only one PWM channel, and create an instance of this driver > for each one of the 8 PWM channels. Then, it could use the pinctrl > framework to dynamically configure the PWM pin it controls. >=20 > Until this can be done, the only jz4740 board supported upstream > (Qi lb60) can configure all of its connected PWM pins in PWM function > mode, since those are not used by other drivers nor by GPIOs on the > board. >=20 > Signed-off-by: Paul Cercueil > --- > drivers/pwm/pwm-jz4740.c | 29 ----------------------------- > 1 file changed, 29 deletions(-) Assuming that you want to take this through the pinctrl tree along with the remainder of the series: Acked-by: Thierry Reding --brEuL7wsLY8+TuWz Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAljmU2EACgkQ3SOs138+ s6HGABAApLsMiPuePBh0cJc9OAijswAsVlj72HCTmH1JA3qrEfhOVWZxltlReNwi z9upRVFfXOAux8PGiJT+0N/z5Zrkwu/haho/al14XxloMx4DSW4UWkeBAVyqBkba N6btN6WY2TLAMi7gav0GWbXFhspUJCncB+HqK2wmXyAhQJfBjMQ2Et1OpniwQ5fe v60TCWUjBY7dZtgtZ5I80tQKjYnZC6hLQoXZcBwTNvQbeIM3sl9cymdPbMXVIJH4 dzxud0NQLfx1flI0KlEI35gpRAAfinGr5XqUYipP1JtsegR51uvpQdQ6l2WdGcBV 9mICw0SZnFuELmPzAYXFjKEYvmOFLB9kMgVHISOgCCwFtJfIH4slY27lZLLvmUkg y/erHU6r8KQfjkVdxNiMcktqMOoAoHaUpWfgsBL/kE3Am0aoXXL3AFEsKY8WXbDg qjN3dsSIdafpEngfpz6tyxbZfPeUkpYubI4+D9T4ov5SC9JeKuPLd6TTXnGtAntx FNhSfWilbcbkYG1r37LpNkW8xWo904JQ7G0pn7opGScBH92xGhV3+g0MBTlTfs/8 t1fqhL3r7+z576vncJwup/hFZq2XrjqCWjizIHKwp2q7vj8JFyN1NXrwRp0CwfJt IwPgbk9MEqstyCKhNIpM4qoJvvmSTQS/SC3k2JvQVGkwjWiytNM= =QxS9 -----END PGP SIGNATURE----- --brEuL7wsLY8+TuWz--