From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753058AbdDHPLI (ORCPT ); Sat, 8 Apr 2017 11:11:08 -0400 Received: from vps0.lunn.ch ([178.209.37.122]:50674 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752995AbdDHPK7 (ORCPT ); Sat, 8 Apr 2017 11:10:59 -0400 Date: Sat, 8 Apr 2017 17:10:50 +0200 From: Andrew Lunn To: David Miller Cc: rogerq@ti.com, tony@atomide.com, nsekhar@ti.com, jsarha@ti.com, netdev@vger.kernel.org, linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] net: davinci_mdio: add GPIO reset logic Message-ID: <20170408151050.GA30797@lunn.ch> References: <1491381237-24635-1-git-send-email-rogerq@ti.com> <20170408.065545.2057882592764132853.davem@davemloft.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170408.065545.2057882592764132853.davem@davemloft.net> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Apr 08, 2017 at 06:55:45AM -0700, David Miller wrote: > From: Roger Quadros > Date: Wed, 5 Apr 2017 11:33:57 +0300 > > > Some boards [1] leave the PHYs at an invalid state > > during system power-up or reset thus causing unreliability > > issues with the PHY like not being detected by the mdio bus > > or link not functional. To work around these boards have > > a GPIO connected to the PHY's reset pin. > > > > Implement GPIO reset handling for such cases. > > > > [1] - am572x-idk, am571x-idk, a437x-idk. > > > > Signed-off-by: Roger Quadros > > Signed-off-by: Sekhar Nori > > I have not seen a resolution in this discussion. > > My understanding is that there are several cases (single MDIO bus whose > reset does a reset on all that MDIO bus's PHYs, etc.) and it's unclear > how to handle all such cases cleanly. I see it falling into two cases. 1) We have a GPIO which resets one PHY. In this case, the GPIO is a PHY property, it should be documented in Documentation/devicetree/bindings/net/phy.txt. Hopefully there is nothing PHY driver specific here, so all the handling can be placed in the core PHY code. 2) We have one or more GPIOs which reset more than one PHY. In this case, the GPIOs are MDIO bus properties. Again, there should not be anything which is MDIO bus driver specific, so all the handling can be placed in the core MDIO bus code. Andrew