From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752731AbdDHRUg (ORCPT ); Sat, 8 Apr 2017 13:20:36 -0400 Received: from mga01.intel.com ([192.55.52.88]:65513 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751517AbdDHRU1 (ORCPT ); Sat, 8 Apr 2017 13:20:27 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,173,1488873600"; d="scan'208";a="843655560" From: Piotr Luc To: linux-edac@vger.kernel.org Cc: Tony Luck , Borislav Petkov , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, linux-kernel@vger.kernel.org, Dave Hansen Subject: [PATCH v1] x86/mce: enable PPIN for Knights Landing/Mill Date: Sat, 8 Apr 2017 19:20:04 +0200 Message-Id: <20170408172004.8463-1-piotr.luc@intel.com> X-Mailer: git-send-email 2.10.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Intel Xeon Phi processors (KNL and KNM) do support PPIN as well, so we add their CPUIDs to the whitelist of supported processors. PPIN is a unique number that allows to determine origin of the CPU, from now on will be logged when an mce error occur. Signed-off-by: Piotr Luc --- arch/x86/kernel/cpu/mcheck/mce_intel.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c index 190b3e6..f1c44c3 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c @@ -481,6 +481,8 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) case INTEL_FAM6_BROADWELL_XEON_D: case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SKYLAKE_X: + case INTEL_FAM6_XEON_PHI_KNL: + case INTEL_FAM6_XEON_PHI_KNM: if (rdmsrl_safe(MSR_PPIN_CTL, &val)) return; -- 2.10.1