linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: linux-pci@vger.kernel.org, bhelgaas@google.com
Cc: linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Arnd Bergmann <arnd@arndb.de>, Will Deacon <will.deacon@arm.com>,
	Russell King <linux@armlinux.org.uk>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Pratyush Anand <pratyush.anand@gmail.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Mingkai Hu <mingkai.hu@freescale.com>,
	John Garry <john.garry@huawei.com>,
	Tanmay Inamdar <tinamdar@apm.com>,
	Murali Karicheri <m-karicheri2@ti.com>,
	Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>,
	Ray Jui <rjui@broadcom.com>, Wenrui Li <wenrui.li@rock-chips.com>,
	Shawn Lin <shawn.lin@rock-chips.com>,
	Minghuan Lian <minghuan.Lian@freescale.com>,
	Jon Mason <jonmason@broadcom.com>,
	Gabriele Paoloni <gabriele.paoloni@huawei.com>,
	Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
	Joao Pinto <Joao.Pinto@synopsys.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	Michal Simek <michal.simek@xilinx.com>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	Zhou Wang <wangzhou1@hisilicon.com>,
	Roy Zang <tie-fei.zang@freescale.com>,
	"Luis R. Rodriguez" <mcgrof@kernel.org>,
	mpe@ellerman.id.au
Subject: Re: [PATCH v4 02/21] linux/io.h: add PCI config space remap interface
Date: Thu, 20 Apr 2017 11:51:53 +0100	[thread overview]
Message-ID: <20170420105153.GA9741@red-moon> (raw)
In-Reply-To: <20170419164913.19674-3-lorenzo.pieralisi@arm.com>

[+ Michael]

On Wed, Apr 19, 2017 at 05:48:51PM +0100, Lorenzo Pieralisi wrote:
> The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and
> Posting") mandate non-posted configuration transactions. As further
> highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering
> Considerations for the Enhanced Configuration Access Mechanism"),
> through ECAM and ECAM-derivative configuration mechanism, the memory
> mapped transactions from the host CPU into Configuration Requests on the
> PCI express fabric may create ordering problems for software because
> writes to memory address are typically posted transactions (unless the
> architecture can enforce through virtual address mapping non-posted
> write transactions behaviour) but writes to Configuration Space are not
> posted on the PCI express fabric.
> 
> Current DT and ACPI host bridge controllers map PCI configuration space
> (ECAM and ECAM-derivative) into the virtual address space through
> ioremap() calls, that are non-cacheable device accesses on most
> architectures, but may provide "bufferable" or "posted" write semantics
> in architecture like eg ARM/ARM64 that allow ioremap'ed regions writes
> to be buffered in the bus connecting the host CPU to the PCI fabric;
> this behaviour, as underlined in the PCIe specifications, may trigger
> transactions ordering rules and must be prevented.
> 
> Introduce a new generic and explicit API to create a memory
> mapping for ECAM and ECAM-derivative config space area that
> defaults to ioremap_nocache() (which should provide a sane default
> behaviour) but still allowing architectures on which ioremap_nocache()
> results in posted write transactions to override the function
> call with an arch specific implementation that complies with
> the PCI specifications for configuration transactions.
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> ---
>  include/linux/io.h | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/include/linux/io.h b/include/linux/io.h
> index 82ef36e..3934aba 100644
> --- a/include/linux/io.h
> +++ b/include/linux/io.h
> @@ -91,6 +91,25 @@ void devm_memunmap(struct device *dev, void *addr);
>  void *__devm_memremap_pages(struct device *dev, struct resource *res);
>  
>  /*
> + * The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and
> + * Posting") mandate non-posted configuration transactions. There is
> + * no ioremap API in the kernel that can guarantee non-posted write
> + * semantics across arches so provide a default implementation for
> + * mapping PCI config space that defaults to ioremap_nocache(); arches
> + * should override it if they have memory mapping implementations that
> + * guarantee non-posted writes semantics to make the memory mapping
> + * compliant with the PCI specification.
> + */
> +#ifndef pci_remap_cfgspace
> +#define pci_remap_cfgspace pci_remap_cfgspace
> +static inline void __iomem *pci_remap_cfgspace(phys_addr_t offset,
> +					       size_t size)
> +{
> +	return ioremap_nocache(offset, size);
> +}
> +#endif
> +
> +/*

As an heads-up, this patch strictly depends on:

https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/arch/powerpc/include/asm/io.h?id=590c369e7ecc00be736be39ae0c62d1b5d563a51

to go upstream first, otherwise we would break powerpc compilation
(owing to powerpc including linux/io.h before ioremap_nocache() is
defined in arch/powerpc/include/asm/io.h).

If we want to decouple them I must drop the static inline and make
it a #define, it is not ideal but we must be aware of this, I really
want to prevent breakage if we go ahead with this set (and -next can
hide the issue).

Thanks,
Lorenzo

>   * Some systems do not have legacy ISA devices.
>   * /dev/port is not a valid interface on these systems.
>   * So for those archs, <asm/io.h> should define the following symbol.
> -- 
> 2.10.0
> 

  reply	other threads:[~2017-04-20 10:51 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-19 16:48 [PATCH v4 00/21] PCI: fix config space memory mappings Lorenzo Pieralisi
2017-04-19 16:48 ` [PATCH v4 01/21] PCI: remove __weak tag from pci_remap_iospace() Lorenzo Pieralisi
2017-04-19 16:48 ` [PATCH v4 02/21] linux/io.h: add PCI config space remap interface Lorenzo Pieralisi
2017-04-20 10:51   ` Lorenzo Pieralisi [this message]
2017-04-20 13:12     ` Bjorn Helgaas
2017-04-19 16:48 ` [PATCH v4 03/21] ARM64: implement pci_remap_cfgspace() interface Lorenzo Pieralisi
2017-04-20 10:33   ` Catalin Marinas
2017-04-19 16:48 ` [PATCH v4 04/21] ARM: " Lorenzo Pieralisi
2017-04-19 16:48 ` [PATCH v4 05/21] lib: fix Devres devm_ioremap_* offset parameter kerneldoc description Lorenzo Pieralisi
2017-04-28 21:20   ` Tejun Heo
2017-04-19 16:48 ` [PATCH v4 06/21] PCI: implement Devres interface to map PCI config space Lorenzo Pieralisi
2017-04-19 16:48 ` [PATCH v4 07/21] PCI: ECAM: use pci_remap_cfgspace() to map config region Lorenzo Pieralisi
2017-04-19 16:48 ` [PATCH v4 08/21] PCI: xilinx: update PCI config space remap function Lorenzo Pieralisi
2017-04-19 16:48 ` [PATCH v4 09/21] PCI: xilinx-nwl: " Lorenzo Pieralisi
2017-04-19 16:48 ` [PATCH v4 10/21] PCI: spear13xx: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 11/21] PCI: rockchip: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 12/21] PCI: qcom: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 13/21] PCI: iproc-platform: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 14/21] PCI: designware: " Lorenzo Pieralisi
2017-04-21 22:02   ` Jingoo Han
2017-04-19 16:49 ` [PATCH v4 15/21] PCI: armada8k: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 16/21] PCI: xgene: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 17/21] PCI: tegra: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 18/21] PCI: hisi: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 19/21] PCI: layerscape: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 20/21] PCI: keystone-dw: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 21/21] PCI: versatile: " Lorenzo Pieralisi
2017-04-20 13:25 ` [PATCH v4 00/21] PCI: fix config space memory mappings Bjorn Helgaas
2017-04-25  6:40 ` Jon Masters
2017-04-25 16:20   ` Jingoo Han
2017-04-25 18:31     ` Khuong Dinh
2017-04-26 10:53   ` Dongdong Liu
2017-04-26 17:24     ` Jingoo Han
2017-04-27  1:46       ` Dongdong Liu
2017-04-27 16:42         ` Khuong Dinh

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20170420105153.GA9741@red-moon \
    --to=lorenzo.pieralisi@arm.com \
    --cc=Joao.Pinto@synopsys.com \
    --cc=arnd@arndb.de \
    --cc=benh@kernel.crashing.org \
    --cc=bharat.kumar.gogada@xilinx.com \
    --cc=bhelgaas@google.com \
    --cc=catalin.marinas@arm.com \
    --cc=gabriele.paoloni@huawei.com \
    --cc=jingoohan1@gmail.com \
    --cc=john.garry@huawei.com \
    --cc=jonmason@broadcom.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux@armlinux.org.uk \
    --cc=m-karicheri2@ti.com \
    --cc=mcgrof@kernel.org \
    --cc=michal.simek@xilinx.com \
    --cc=minghuan.Lian@freescale.com \
    --cc=mingkai.hu@freescale.com \
    --cc=mpe@ellerman.id.au \
    --cc=pratyush.anand@gmail.com \
    --cc=rjui@broadcom.com \
    --cc=shawn.lin@rock-chips.com \
    --cc=svarbanov@mm-sol.com \
    --cc=thierry.reding@gmail.com \
    --cc=thomas.petazzoni@free-electrons.com \
    --cc=tie-fei.zang@freescale.com \
    --cc=tinamdar@apm.com \
    --cc=wangzhou1@hisilicon.com \
    --cc=wenrui.li@rock-chips.com \
    --cc=will.deacon@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).