From: Florian Fainelli <f.fainelli@gmail.com>
To: linux-arm-kernel@lists.infradead.org
Cc: alcooperx@gmail.com, opendmb@gmail.com,
Florian Fainelli <f.fainelli@gmail.com>,
Will Deacon <will.deacon@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Catalin Marinas <catalin.marinas@arm.com>,
linux-kernel@vger.kernel.org (open list:PERFORMANCE EVENTS
SUBSYSTEM)
Subject: [PATCH 1/2] arm64: perf: Wire-up Cortex A53 L2 cache events and DTLB refills
Date: Thu, 20 Apr 2017 12:05:44 -0700 [thread overview]
Message-ID: <20170420190546.7453-2-f.fainelli@gmail.com> (raw)
In-Reply-To: <20170420190546.7453-1-f.fainelli@gmail.com>
Add missing L2 cache events: read/write accesses and misses, as well as
the DTLB refills.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm64/kernel/perf_event.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 57ae9d9ed9bb..4f011cdd756d 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -290,6 +290,12 @@ static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
+ [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
+ [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
+ [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
+ [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
+
+ [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
--
2.9.3
next prev parent reply other threads:[~2017-04-20 19:06 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-20 19:05 [PATCH 0/2] arm64: perf: Add L2 cache events for ARMv8 PMuv3 and A53 Florian Fainelli
2017-04-20 19:05 ` Florian Fainelli [this message]
2017-04-20 19:05 ` [PATCH 1/2] arm64: pmu: Wire-up Cortex A53 L2 cache events and DTLB refills Florian Fainelli
2017-04-20 19:05 ` [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 Florian Fainelli
2017-04-25 12:44 ` Will Deacon
2017-04-25 17:13 ` Florian Fainelli
2017-04-27 17:36 ` Will Deacon
2017-04-28 14:15 ` Catalin Marinas
2017-04-28 14:17 ` Will Deacon
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