* [PATCH 0/2] arm64: perf: Add L2 cache events for ARMv8 PMuv3 and A53
@ 2017-04-20 19:05 Florian Fainelli
2017-04-20 19:05 ` [PATCH 1/2] arm64: perf: Wire-up Cortex A53 L2 cache events and DTLB refills Florian Fainelli
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Florian Fainelli @ 2017-04-20 19:05 UTC (permalink / raw)
To: linux-arm-kernel
Cc: alcooperx, opendmb, Florian Fainelli, Will Deacon, Mark Rutland,
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Alexander Shishkin, Catalin Marinas,
open list:PERFORMANCE EVENTS SUBSYSTEM
Hi,
While investigating why there were no L2 cache events generated for a Cortex
A53-like PMU, it turned out that none of the L2 cache events were mapped.
This is also the case for ARMv8 PMUv3, which seems a little odd considering
they are defined.
Thanks!
Florian Fainelli (2):
arm64: perf: Wire-up Cortex A53 L2 cache events and DTLB refills
arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3
arch/arm64/kernel/perf_event.c | 11 +++++++++++
1 file changed, 11 insertions(+)
--
2.9.3
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/2] arm64: perf: Wire-up Cortex A53 L2 cache events and DTLB refills
2017-04-20 19:05 [PATCH 0/2] arm64: perf: Add L2 cache events for ARMv8 PMuv3 and A53 Florian Fainelli
@ 2017-04-20 19:05 ` Florian Fainelli
2017-04-20 19:05 ` [PATCH 1/2] arm64: pmu: " Florian Fainelli
2017-04-20 19:05 ` [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 Florian Fainelli
2 siblings, 0 replies; 9+ messages in thread
From: Florian Fainelli @ 2017-04-20 19:05 UTC (permalink / raw)
To: linux-arm-kernel
Cc: alcooperx, opendmb, Florian Fainelli, Will Deacon, Mark Rutland,
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Alexander Shishkin, Catalin Marinas,
open list:PERFORMANCE EVENTS SUBSYSTEM
Add missing L2 cache events: read/write accesses and misses, as well as
the DTLB refills.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm64/kernel/perf_event.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 57ae9d9ed9bb..4f011cdd756d 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -290,6 +290,12 @@ static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
+ [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
+ [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
+ [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
+ [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
+
+ [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
--
2.9.3
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 1/2] arm64: pmu: Wire-up Cortex A53 L2 cache events and DTLB refills
2017-04-20 19:05 [PATCH 0/2] arm64: perf: Add L2 cache events for ARMv8 PMuv3 and A53 Florian Fainelli
2017-04-20 19:05 ` [PATCH 1/2] arm64: perf: Wire-up Cortex A53 L2 cache events and DTLB refills Florian Fainelli
@ 2017-04-20 19:05 ` Florian Fainelli
2017-04-20 19:05 ` [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 Florian Fainelli
2 siblings, 0 replies; 9+ messages in thread
From: Florian Fainelli @ 2017-04-20 19:05 UTC (permalink / raw)
To: linux-arm-kernel
Cc: alcooperx, opendmb, Florian Fainelli, Will Deacon, Mark Rutland,
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Alexander Shishkin, Catalin Marinas,
open list:PERFORMANCE EVENTS SUBSYSTEM
Add missing L2 cache events: read/write accesses and misses, as well as
the DTLB refills.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm64/kernel/perf_event.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 57ae9d9ed9bb..4f011cdd756d 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -290,6 +290,12 @@ static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
+ [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
+ [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
+ [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
+ [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
+
+ [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
--
2.9.3
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3
2017-04-20 19:05 [PATCH 0/2] arm64: perf: Add L2 cache events for ARMv8 PMuv3 and A53 Florian Fainelli
2017-04-20 19:05 ` [PATCH 1/2] arm64: perf: Wire-up Cortex A53 L2 cache events and DTLB refills Florian Fainelli
2017-04-20 19:05 ` [PATCH 1/2] arm64: pmu: " Florian Fainelli
@ 2017-04-20 19:05 ` Florian Fainelli
2017-04-25 12:44 ` Will Deacon
2 siblings, 1 reply; 9+ messages in thread
From: Florian Fainelli @ 2017-04-20 19:05 UTC (permalink / raw)
To: linux-arm-kernel
Cc: alcooperx, opendmb, Florian Fainelli, Will Deacon, Mark Rutland,
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Alexander Shishkin, Catalin Marinas,
open list:PERFORMANCE EVENTS SUBSYSTEM
The ARMv8 PMUv3 cache map did not include the L2 cache events, add
them.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm64/kernel/perf_event.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 4f011cdd756d..a664c575f3fd 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -264,6 +264,11 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
+ [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
+ [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
+ [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
+ [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
+
[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
[C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
--
2.9.3
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3
2017-04-20 19:05 ` [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 Florian Fainelli
@ 2017-04-25 12:44 ` Will Deacon
2017-04-25 17:13 ` Florian Fainelli
0 siblings, 1 reply; 9+ messages in thread
From: Will Deacon @ 2017-04-25 12:44 UTC (permalink / raw)
To: Florian Fainelli
Cc: linux-arm-kernel, alcooperx, opendmb, Mark Rutland,
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Alexander Shishkin, Catalin Marinas,
open list:PERFORMANCE EVENTS SUBSYSTEM
Hi Florian,
On Thu, Apr 20, 2017 at 12:05:46PM -0700, Florian Fainelli wrote:
> The ARMv8 PMUv3 cache map did not include the L2 cache events, add
> them.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> arch/arm64/kernel/perf_event.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index 4f011cdd756d..a664c575f3fd 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -264,6 +264,11 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
> [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
> [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
>
> + [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
> + [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
> + [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
> + [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
I don't think this is correct in general. 'LL' stands for "last-level",
which may be L3 or even a system cache in the interconnect. Tying that to L2
is the wrong thing to do from perf's generic event perspective.
I'm ok with what you're proposing for A53 (where the PMU can only count
events out to the L2), but I'm reluctant to make this change for the generic
PMUv3 events.
Will
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3
2017-04-25 12:44 ` Will Deacon
@ 2017-04-25 17:13 ` Florian Fainelli
2017-04-27 17:36 ` Will Deacon
0 siblings, 1 reply; 9+ messages in thread
From: Florian Fainelli @ 2017-04-25 17:13 UTC (permalink / raw)
To: Will Deacon
Cc: linux-arm-kernel, alcooperx, opendmb, Mark Rutland,
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Alexander Shishkin, Catalin Marinas,
open list:PERFORMANCE EVENTS SUBSYSTEM
On 04/25/2017 05:44 AM, Will Deacon wrote:
> Hi Florian,
>
> On Thu, Apr 20, 2017 at 12:05:46PM -0700, Florian Fainelli wrote:
>> The ARMv8 PMUv3 cache map did not include the L2 cache events, add
>> them.
>>
>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>> ---
>> arch/arm64/kernel/perf_event.c | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
>> index 4f011cdd756d..a664c575f3fd 100644
>> --- a/arch/arm64/kernel/perf_event.c
>> +++ b/arch/arm64/kernel/perf_event.c
>> @@ -264,6 +264,11 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
>> [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
>> [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
>>
>> + [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
>> + [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
>> + [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
>> + [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
>
> I don't think this is correct in general. 'LL' stands for "last-level",
> which may be L3 or even a system cache in the interconnect. Tying that to L2
> is the wrong thing to do from perf's generic event perspective.
>
> I'm ok with what you're proposing for A53 (where the PMU can only count
> events out to the L2), but I'm reluctant to make this change for the generic
> PMUv3 events.
That makes sense, shall I resubmit the first patch by itself or can you
or Catalin take it as-is?
Thanks!
--
Florian
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3
2017-04-25 17:13 ` Florian Fainelli
@ 2017-04-27 17:36 ` Will Deacon
2017-04-28 14:15 ` Catalin Marinas
0 siblings, 1 reply; 9+ messages in thread
From: Will Deacon @ 2017-04-27 17:36 UTC (permalink / raw)
To: Florian Fainelli
Cc: linux-arm-kernel, alcooperx, opendmb, Mark Rutland,
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Alexander Shishkin, Catalin Marinas,
open list:PERFORMANCE EVENTS SUBSYSTEM
On Tue, Apr 25, 2017 at 10:13:51AM -0700, Florian Fainelli wrote:
> On 04/25/2017 05:44 AM, Will Deacon wrote:
> > Hi Florian,
> >
> > On Thu, Apr 20, 2017 at 12:05:46PM -0700, Florian Fainelli wrote:
> >> The ARMv8 PMUv3 cache map did not include the L2 cache events, add
> >> them.
> >>
> >> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> >> ---
> >> arch/arm64/kernel/perf_event.c | 5 +++++
> >> 1 file changed, 5 insertions(+)
> >>
> >> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> >> index 4f011cdd756d..a664c575f3fd 100644
> >> --- a/arch/arm64/kernel/perf_event.c
> >> +++ b/arch/arm64/kernel/perf_event.c
> >> @@ -264,6 +264,11 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
> >> [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
> >> [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
> >>
> >> + [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
> >> + [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
> >> + [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
> >> + [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
> >
> > I don't think this is correct in general. 'LL' stands for "last-level",
> > which may be L3 or even a system cache in the interconnect. Tying that to L2
> > is the wrong thing to do from perf's generic event perspective.
> >
> > I'm ok with what you're proposing for A53 (where the PMU can only count
> > events out to the L2), but I'm reluctant to make this change for the generic
> > PMUv3 events.
>
> That makes sense, shall I resubmit the first patch by itself or can you
> or Catalin take it as-is?
I'll talk to Catalin tomorrow and try to get the A53 bit queued.
Will
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3
2017-04-27 17:36 ` Will Deacon
@ 2017-04-28 14:15 ` Catalin Marinas
2017-04-28 14:17 ` Will Deacon
0 siblings, 1 reply; 9+ messages in thread
From: Catalin Marinas @ 2017-04-28 14:15 UTC (permalink / raw)
To: Will Deacon
Cc: Florian Fainelli, Mark Rutland, opendmb, Peter Zijlstra,
alcooperx, open list:PERFORMANCE EVENTS SUBSYSTEM,
Arnaldo Carvalho de Melo, Alexander Shishkin, Ingo Molnar,
linux-arm-kernel
On Thu, Apr 27, 2017 at 06:36:42PM +0100, Will Deacon wrote:
> On Tue, Apr 25, 2017 at 10:13:51AM -0700, Florian Fainelli wrote:
> > On 04/25/2017 05:44 AM, Will Deacon wrote:
> > > On Thu, Apr 20, 2017 at 12:05:46PM -0700, Florian Fainelli wrote:
> > >> The ARMv8 PMUv3 cache map did not include the L2 cache events, add
> > >> them.
> > >>
> > >> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> > >> ---
> > >> arch/arm64/kernel/perf_event.c | 5 +++++
> > >> 1 file changed, 5 insertions(+)
> > >>
> > >> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> > >> index 4f011cdd756d..a664c575f3fd 100644
> > >> --- a/arch/arm64/kernel/perf_event.c
> > >> +++ b/arch/arm64/kernel/perf_event.c
> > >> @@ -264,6 +264,11 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
> > >> [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
> > >> [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
> > >>
> > >> + [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
> > >> + [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
> > >> + [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
> > >> + [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
> > >
> > > I don't think this is correct in general. 'LL' stands for "last-level",
> > > which may be L3 or even a system cache in the interconnect. Tying that to L2
> > > is the wrong thing to do from perf's generic event perspective.
> > >
> > > I'm ok with what you're proposing for A53 (where the PMU can only count
> > > events out to the L2), but I'm reluctant to make this change for the generic
> > > PMUv3 events.
> >
> > That makes sense, shall I resubmit the first patch by itself or can you
> > or Catalin take it as-is?
>
> I'll talk to Catalin tomorrow and try to get the A53 bit queued.
I queued patch 1/2. Shall I add your ack?
--
Catalin
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3
2017-04-28 14:15 ` Catalin Marinas
@ 2017-04-28 14:17 ` Will Deacon
0 siblings, 0 replies; 9+ messages in thread
From: Will Deacon @ 2017-04-28 14:17 UTC (permalink / raw)
To: Catalin Marinas
Cc: Florian Fainelli, Mark Rutland, opendmb, Peter Zijlstra,
alcooperx, open list:PERFORMANCE EVENTS SUBSYSTEM,
Arnaldo Carvalho de Melo, Alexander Shishkin, Ingo Molnar,
linux-arm-kernel
On Fri, Apr 28, 2017 at 03:15:01PM +0100, Catalin Marinas wrote:
> On Thu, Apr 27, 2017 at 06:36:42PM +0100, Will Deacon wrote:
> > On Tue, Apr 25, 2017 at 10:13:51AM -0700, Florian Fainelli wrote:
> > > On 04/25/2017 05:44 AM, Will Deacon wrote:
> > > > On Thu, Apr 20, 2017 at 12:05:46PM -0700, Florian Fainelli wrote:
> > > >> The ARMv8 PMUv3 cache map did not include the L2 cache events, add
> > > >> them.
> > > >>
> > > >> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> > > >> ---
> > > >> arch/arm64/kernel/perf_event.c | 5 +++++
> > > >> 1 file changed, 5 insertions(+)
> > > >>
> > > >> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> > > >> index 4f011cdd756d..a664c575f3fd 100644
> > > >> --- a/arch/arm64/kernel/perf_event.c
> > > >> +++ b/arch/arm64/kernel/perf_event.c
> > > >> @@ -264,6 +264,11 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
> > > >> [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
> > > >> [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
> > > >>
> > > >> + [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
> > > >> + [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
> > > >> + [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE,
> > > >> + [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL,
> > > >
> > > > I don't think this is correct in general. 'LL' stands for "last-level",
> > > > which may be L3 or even a system cache in the interconnect. Tying that to L2
> > > > is the wrong thing to do from perf's generic event perspective.
> > > >
> > > > I'm ok with what you're proposing for A53 (where the PMU can only count
> > > > events out to the L2), but I'm reluctant to make this change for the generic
> > > > PMUv3 events.
> > >
> > > That makes sense, shall I resubmit the first patch by itself or can you
> > > or Catalin take it as-is?
> >
> > I'll talk to Catalin tomorrow and try to get the A53 bit queued.
>
> I queued patch 1/2. Shall I add your ack?
Yes, please.
Will
^ permalink raw reply [flat|nested] 9+ messages in thread
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2017-04-20 19:05 [PATCH 0/2] arm64: perf: Add L2 cache events for ARMv8 PMuv3 and A53 Florian Fainelli
2017-04-20 19:05 ` [PATCH 1/2] arm64: perf: Wire-up Cortex A53 L2 cache events and DTLB refills Florian Fainelli
2017-04-20 19:05 ` [PATCH 1/2] arm64: pmu: " Florian Fainelli
2017-04-20 19:05 ` [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 Florian Fainelli
2017-04-25 12:44 ` Will Deacon
2017-04-25 17:13 ` Florian Fainelli
2017-04-27 17:36 ` Will Deacon
2017-04-28 14:15 ` Catalin Marinas
2017-04-28 14:17 ` Will Deacon
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