From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1434555AbdDZOlV (ORCPT ); Wed, 26 Apr 2017 10:41:21 -0400 Received: from foss.arm.com ([217.140.101.70]:56934 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1040667AbdDZOlL (ORCPT ); Wed, 26 Apr 2017 10:41:11 -0400 Date: Wed, 26 Apr 2017 15:41:08 +0100 From: Liviu Dudau To: Arnd Bergmann Cc: Brian Starkey , Mali DP Maintainers , David Airlie , Mihail Atanassov , Daniel Vetter , Shawn Guo , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] drm: mali-dp: use div_u64 for expensive 64-bit divisions Message-ID: <20170426144108.GD7170@e110455-lin.cambridge.arm.com> Mail-Followup-To: Arnd Bergmann , Brian Starkey , Mali DP Maintainers , David Airlie , Mihail Atanassov , Daniel Vetter , Shawn Guo , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20170425195712.2017230-1-arnd@arndb.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20170425195712.2017230-1-arnd@arndb.de> User-Agent: Mutt/1.8.2 (2017-04-18) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 25, 2017 at 09:56:53PM +0200, Arnd Bergmann wrote: > On 32-bit machines, we can't divide 64-bit integers: > > drivers/gpu/drm/arm/malidp_crtc.o: In function `malidp_crtc_atomic_check': > malidp_crtc.c:(.text.malidp_crtc_atomic_check+0x3c0): undefined reference to `__aeabi_uldivmod' > malidp_crtc.c:(.text.malidp_crtc_atomic_check+0x3dc): undefined reference to `__aeabi_uldivmod' > > This calls the div_u64 function explicitly instead. > > Fixes: 4cea4e9f6690 ("drm: mali-dp: Add plane upscaling support") > Signed-off-by: Arnd Bergmann Acked-by: Liviu Dudau I'll push the patch to the mali-dp repository. Dave A., if you have pulled the mali-dp patches then this will need to go in as well, otherwise I will send an updated pull request soon. Best regards, Liviu > --- > drivers/gpu/drm/arm/malidp_crtc.c | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c > index 19f1f3b34691..9446a673d469 100644 > --- a/drivers/gpu/drm/arm/malidp_crtc.c > +++ b/drivers/gpu/drm/arm/malidp_crtc.c > @@ -266,7 +266,6 @@ static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc, > > drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { > struct malidp_plane *mp = to_malidp_plane(plane); > - u64 crtc_w, crtc_h; > u32 phase; > > if (!(mp->layer->id & scaling)) > @@ -276,10 +275,10 @@ static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc, > * Convert crtc_[w|h] to U32.32, then divide by U16.16 src_[w|h] > * to get the U16.16 result. > */ > - crtc_w = (u64)pstate->crtc_w << 32; > - crtc_h = (u64)pstate->crtc_h << 32; > - h_upscale_factor = (u32)(crtc_w / pstate->src_w); > - v_upscale_factor = (u32)(crtc_h / pstate->src_h); > + h_upscale_factor = div_u64((u64)pstate->crtc_w << 32, > + pstate->src_w); > + v_upscale_factor = div_u64((u64)pstate->crtc_h << 32, > + pstate->src_h); > > s->enhancer_enable = ((h_upscale_factor >> 16) >= 2 || > (v_upscale_factor >> 16) >= 2); > -- > 2.9.0 > -- ==================== | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --------------- ¯\_(ツ)_/¯