From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S939226AbdD0N20 (ORCPT ); Thu, 27 Apr 2017 09:28:26 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:39777 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934072AbdD0N2R (ORCPT ); Thu, 27 Apr 2017 09:28:17 -0400 Date: Thu, 27 Apr 2017 15:28:05 +0200 From: Maxime Ripard To: Icenowy Zheng Cc: Thomas Gleixner , Rob Herring , Chen-Yu Tsai , Lee Jones , Liam Girdwood , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH v5 01/10] arm64: allwinner: a64: enable RSB on A64 Message-ID: <20170427132805.izv6xfktlhfc4yty@lukather> References: <20170426152023.41567-1-icenowy@aosc.io> <20170426152023.41567-2-icenowy@aosc.io> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="vmgrw4du3ohy337q" Content-Disposition: inline In-Reply-To: <20170426152023.41567-2-icenowy@aosc.io> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --vmgrw4du3ohy337q Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Apr 26, 2017 at 11:20:14PM +0800, Icenowy Zheng wrote: > Allwinner A64 have a RSB controller like the one on A23/A33 SoCs. >=20 > Add it and its pinmux. >=20 > Signed-off-by: Icenowy Zheng > Acked-by: Chen-Yu Tsai > --- > Changes in v2: > - Removed bonus properties in pio node. > - Added Chen-Yu's ACK. >=20 > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/b= oot/dts/allwinner/sun50i-a64.dtsi > index c7f669f5884f..05ec9fc5e81f 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > @@ -422,6 +422,25 @@ > #gpio-cells =3D <3>; > interrupt-controller; > #interrupt-cells =3D <3>; > + > + r_rsb_pins: rsb@0 { > + pins =3D "PL0", "PL1"; > + function =3D "s_rsb"; > + }; > + }; > + > + r_rsb: rsb@1f03400 { > + compatible =3D "allwinner,sun8i-a23-rsb"; > + reg =3D <0x01f03400 0x400>; > + interrupts =3D ; > + clocks =3D <&r_ccu 6>; Please use the defines here.. > + clock-frequency =3D <3000000>; > + resets =3D <&r_ccu 2>; And here. Thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --vmgrw4du3ohy337q Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIcBAABCAAGBQJZAfHiAAoJEBx+YmzsjxAgAsYP/2Nj0i4mzSliuHS4kLEdEpeF LxYjEWpghrcLtV4oHr/ow4rK3VNlcom5OucUmLqpupmQZWv7ZKuD4gRJ74yf0zhg yzoq2xNDjFBdrV6d68hKzjyXlATXAfEq43wODvvUcrmyiP/a8u4SZmZBDT94QLaP mh0UGVwKhZFRdhKiMQ/eHwhpTyMbWKVOj91Hrqb+Obnmb4zXaas/7FWHuZV6ibL1 kxVp+1BMcESOBlN+CCphcGSLZF+F0gS+FKKHn7NeyzSp6/Cp3ZYYPlGz1UU+K/QJ oVs2o3sR616WU2uO/1aP/sDyKy87hJZHnECr+NPjZVigt5MokKYjoy7bSbG5sGJO XHDbVvxNQvw5/H1aAzwuAcssn6/KP6rCt8nEhZ55jIxUeH1oSRhL9xaIWNjtJWlN CwIlmoQZSA2F1aAazyCsxJrV7RcexDK/cWeWDkXPAHhtqhgILiJ5s7KjmDsTRI5p 2PX6qKMZLqrGfAQFz1fM93K6LS1eiwOrnhR012m7yMXw3+hWN61IgNyUvhxo1pyY dTA+Qs4vJoFMcwdXJpwmfxS5u3wFfX7Fakwxii8zZIQ2HbZnNttFXDONDF88ZRGf 8WVm2XUnDCzJDTD7uEHm8PoV2IoJ0XjKgZi/CT3k8WFODMGceF9OZRDfporCIwYI OZvj1vfcKctvYPbpxxCF =R/kK -----END PGP SIGNATURE----- --vmgrw4du3ohy337q--