From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1425319AbdD1SyB (ORCPT ); Fri, 28 Apr 2017 14:54:01 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:32946 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1035513AbdD1Sxw (ORCPT ); Fri, 28 Apr 2017 14:53:52 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E23A060779 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Fri, 28 Apr 2017 11:53:49 -0700 From: Stephen Boyd To: Varadarajan Narayanan Cc: robh+dt@kernel.org, mark.rutland@arm.com, mturquette@baylibre.com, linus.walleij@linaro.org, andy.gross@linaro.org, david.brown@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, sricharan@codeaurora.org, absahu@codeaurora.org, sjaganat@codeaurora.org, Manoharan Vijaya Raghavan Subject: Re: [PATCH 4/5] arm64: dts: Add ipq8074 SoC and MTP board support Message-ID: <20170428185349.GD7065@codeaurora.org> References: <1493373403-23462-1-git-send-email-varada@codeaurora.org> <1493373403-23462-5-git-send-email-varada@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1493373403-23462-5-git-send-email-varada@codeaurora.org> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/28, Varadarajan Narayanan wrote: > diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts > new file mode 100644 > index 0000000..c150bea > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts > @@ -0,0 +1,48 @@ > +/dts-v1/; > +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 and > + * only version 2 as published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > +#include "ipq8074.dtsi" > + > +/ { > + #address-cells = <0x2>; > + #size-cells = <0x2>; > + model = "Qualcomm Technologies, Inc. IPQ8074-HK01"; > + compatible = "qcom,ipq8074-hk01", "qcom,ipq8074"; > + interrupt-parent = <&intc>; > + > + chosen { > + bootargs = "console=ttyMSM0,115200,n8 root=/dev/ram0 rw init=/init"; Add an aliases node for serial0 and use a chosen node with stdout-path = "serial0" instead please. > + }; > + > + memory { > + device_type = "memory"; > + reg = <0x0 0x40000000 0x0 0x20000000>; > + }; > + > + soc: soc { Do you need the soc label here? Please remove. > + pinctrl@1000000 { > + serial_4_pins: serial4_pinmux { > + mux { > + pins = "gpio23", "gpio24"; > + function = "blsp4_uart1"; > + bias-disable; > + }; > + }; > + }; > + > + serial@78b3000 { > + pinctrl-0 = <&serial_4_pins>; > + pinctrl-names = "default"; > + status = "ok"; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi > new file mode 100644 > index 0000000..f910cc0 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi > @@ -0,0 +1,153 @@ > +/* > + * Copyright (c) 2017, The Linux Foundation. All rights reserved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 and > + * only version 2 as published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include > +#include > + > +/ { > + model = "Qualcomm Technologies, Inc. IPQ8074"; > + compatible = "qcom,ipq8074"; > + > + soc: soc { > + #address-cells = <0x1>; > + #size-cells = <0x1>; > + ranges = <0 0 0 0xffffffff>; > + compatible = "simple-bus"; > + > + pinctrl@1000000 { > + compatible = "qcom,ipq8074-pinctrl"; > + reg = <0x1000000 0x300000>; > + interrupts = ; > + gpio-controller; > + #gpio-cells = <0x2>; > + interrupt-controller; > + #interrupt-cells = <0x2>; > + }; > + > + intc: interrupt-controller@b000000 { > + compatible = "qcom,msm-qgic2"; > + interrupt-controller; > + #interrupt-cells = <0x3>; > + reg = <0xb000000 0x1000>, > + <0xb002000 0x1000>; Please align this up with previous reg property. > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; > + }; Is there an mmio timer as well? We should add it too. > + > + gcc: gcc@1800000 { > + compatible = "qcom,gcc-ipq8074"; > + reg = <0x1800000 0x80000>; Wow that is a huge area! Is it really that large? > + #clock-cells = <0x1>; > + #reset-cells = <0x1>; > + }; > + > + serial@78b3000 { > + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; > + reg = <0x78b3000 0x200>; > + interrupts = ; > + clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, > + <&gcc GCC_BLSP1_AHB_CLK>; > + clock-names = "core", "iface"; > + status = "disabled"; > + }; > + }; > + > + cpus { > + #address-cells = <0x1>; > + #size-cells = <0x0>; > + > + cpu-map { > + > + cluster0 { > + > + core0 { > + cpu = <&CPU0>; > + }; > + > + core1 { > + cpu = <&CPU1>; > + }; > + > + core2 { > + cpu = <&CPU2>; > + }; > + > + core3 { > + cpu = <&CPU3>; > + }; > + }; > + }; Is this needed? Looks ok, but just curious if we need to do it for other arm64 platforms we support. > + > + CPU0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0>; > + next-level-cache = <&L2_0>; > + enable-method = "psci"; > + }; > + > + CPU1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + enable-method = "psci"; > + reg = <0x1>; > + next-level-cache = <&L2_0>; > + }; > + > + CPU2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + enable-method = "psci"; > + reg = <0x2>; > + next-level-cache = <&L2_0>; > + }; > + > + CPU3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + enable-method = "psci"; > + reg = <0x3>; > + next-level-cache = <&L2_0>; > + }; > + > + L2_0: l2-cache { > + compatible = "cache"; > + cache-level = <0x2>; > + }; This should be inside some CPU? CPU0? > + }; We should be able to add the performance monitor node too? > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + clocks { > + sleep_clk: sleep_clk { > + compatible = "fixed-clock"; > + clock-frequency = <32000>; Not 32765 or 32768? > + #clock-cells = <0>; > + }; > + > + xo: xo { > + compatible = "fixed-clock"; > + clock-frequency = <19200000>; > + #clock-cells = <0>; > + }; > + }; -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project