From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753659AbdEINt2 (ORCPT ); Tue, 9 May 2017 09:49:28 -0400 Received: from mail-by2nam03on0073.outbound.protection.outlook.com ([104.47.42.73]:15584 "EHLO NAM03-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751304AbdEINtZ (ORCPT ); Tue, 9 May 2017 09:49:25 -0400 Authentication-Results: arm.com; dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=cavium.com; Date: Tue, 9 May 2017 19:18:56 +0530 From: Linu Cherian To: Robin Murphy Cc: Geetha sowjanya , will.deacon@arm.com, lorenzo.pieralisi@arm.com, hanjun.guo@linaro.org, sudeep.holla@arm.com, iommu@lists.linux-foundation.org, jcm@redhat.com, linux-kernel@vger.kernel.org, robert.richter@cavium.com, catalin.marinas@arm.com, sgoutham@cavium.com, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, geethasowjanya.akula@gmail.com, Charles.Garcia-Tobin@arm.com, Geetha Sowjanya Subject: Re: [v4 3/4] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Message-ID: <20170509134856.GA1090@virtx40> References: <1494330314-30179-1-git-send-email-gakula@caviumnetworks.com> <1494330314-30179-4-git-send-email-gakula@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Originating-IP: [111.93.218.67] X-ClientProxiedBy: PN1PR01CA0101.INDPRD01.PROD.OUTLOOK.COM (10.174.144.17) To CO2PR07MB2519.namprd07.prod.outlook.com (10.166.201.6) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6733d0e1-5e42-4dd0-9795-08d496e232ed X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(201703131423075)(201703031133081);SRVR:CO2PR07MB2519; X-Microsoft-Exchange-Diagnostics: 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SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1;CO2PR07MB2519;7:N073LEhSo5vyKZIriz027WWEVa0FXGnmGHsAeGKtV2SDD+BTw41+CitGJ6MfJ+iZd7pPM9VI0ibpPnqEqEoidzMNR+W8QoKsJzdqJjU0AJ5MEu+aB9McfYwjf5BDNKKbdpa5BinRKGFFSDUpN5QSkLThE/LE6qzCxfajUFq5xylYLU44SZxecen0TG1/yAlU3bJGpgjWvHJNK9K0+Kili3y6y7cX9ov5kT7se4UR7c4L63McguWzD3cCmAgWW9Dyagw5CRvb/ZLPL5lUsj32KWigT9hPa01TOmFFn9wKTcPqtMutlDeIN8D0nK6bpyvFwjdD02HHgc4HorS1iXtMIQ== X-OriginatorOrg: cavium.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2017 13:49:17.4865 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO2PR07MB2519 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue May 09, 2017 at 02:02:58PM +0100, Robin Murphy wrote: > On 09/05/17 12:45, Geetha sowjanya wrote: > > From: Linu Cherian > > > > Cavium ThunderX2 SMMU implementation doesn't support page 1 register space > > and PAGE0_REGS_ONLY option is enabled as an errata workaround. > > This option when turned on, replaces all page 1 offsets used for > > EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets. > > > > SMMU resource size checks are now based on SMMU option PAGE0_REGS_ONLY, > > since resource size can be either 64k/128k. > > For this, arm_smmu_device_dt_probe/acpi_probe has been moved before > > platform_get_resource call, so that SMMU options are set beforehand. > > > > Signed-off-by: Linu Cherian > > Signed-off-by: Geetha Sowjanya > > --- > > Documentation/arm64/silicon-errata.txt | 1 + > > .../devicetree/bindings/iommu/arm,smmu-v3.txt | 6 ++ > > drivers/iommu/arm-smmu-v3.c | 80 ++++++++++++++++------ > > 3 files changed, 66 insertions(+), 21 deletions(-) > > > > diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt > > index 10f2ddd..4693a32 100644 > > --- a/Documentation/arm64/silicon-errata.txt > > +++ b/Documentation/arm64/silicon-errata.txt > > @@ -62,6 +62,7 @@ stable kernels. > > | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | > > | Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | > > | Cavium | ThunderX SMMUv2 | #27704 | N/A | > > +| Cavium | ThunderX2 SMMUv3| #74 | N/A | > > | | | | | > > | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | > > | | | | | > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt > > index be57550..e6da62b 100644 > > --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt > > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt > > @@ -49,6 +49,12 @@ the PCIe specification. > > - hisilicon,broken-prefetch-cmd > > : Avoid sending CMD_PREFETCH_* commands to the SMMU. > > > > +- cavium-cn99xx,broken-page1-regspace > > + : Replaces all page 1 offsets used for EVTQ_PROD/CONS, > > + PRIQ_PROD/CONS register access with page 0 offsets. > > + Set for Caviun ThunderX2 silicon that doesn't support > > + SMMU page1 register space. > > + > > ** Example > > > > smmu@2b400000 { > > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c > > index 380969a..1e986a0 100644 > > --- a/drivers/iommu/arm-smmu-v3.c > > +++ b/drivers/iommu/arm-smmu-v3.c > > @@ -176,15 +176,15 @@ > > #define ARM_SMMU_CMDQ_CONS 0x9c > > > > #define ARM_SMMU_EVTQ_BASE 0xa0 > > -#define ARM_SMMU_EVTQ_PROD 0x100a8 > > -#define ARM_SMMU_EVTQ_CONS 0x100ac > > +#define ARM_SMMU_EVTQ_PROD(smmu) (page1_offset_adjust(0x100a8, smmu)) > > +#define ARM_SMMU_EVTQ_CONS(smmu) (page1_offset_adjust(0x100ac, smmu)) > > Sorry, perhaps I should have communicated the rest of the idea more > explicitly - you now don't need to change these definitions... > Fine. > > #define ARM_SMMU_EVTQ_IRQ_CFG0 0xb0 > > #define ARM_SMMU_EVTQ_IRQ_CFG1 0xb8 > > #define ARM_SMMU_EVTQ_IRQ_CFG2 0xbc > > > > #define ARM_SMMU_PRIQ_BASE 0xc0 > > -#define ARM_SMMU_PRIQ_PROD 0x100c8 > > -#define ARM_SMMU_PRIQ_CONS 0x100cc > > +#define ARM_SMMU_PRIQ_PROD(smmu) (page1_offset_adjust(0x100c8, smmu)) > > +#define ARM_SMMU_PRIQ_CONS(smmu) (page1_offset_adjust(0x100cc, smmu)) > > #define ARM_SMMU_PRIQ_IRQ_CFG0 0xd0 > > #define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8 > > #define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc > > @@ -412,6 +412,9 @@ > > #define MSI_IOVA_BASE 0x8000000 > > #define MSI_IOVA_LENGTH 0x100000 > > > > +#define ARM_SMMU_PAGE0_REGS_ONLY(smmu) \ > > + ((smmu)->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY) > > + > > static bool disable_bypass; > > module_param_named(disable_bypass, disable_bypass, bool, S_IRUGO); > > MODULE_PARM_DESC(disable_bypass, > > @@ -597,6 +600,7 @@ struct arm_smmu_device { > > u32 features; > > > > #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) > > +#define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) > > u32 options; > > > > struct arm_smmu_cmdq cmdq; > > @@ -663,9 +667,19 @@ struct arm_smmu_option_prop { > > > > static struct arm_smmu_option_prop arm_smmu_options[] = { > > { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" }, > > + { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium-cn99xx,broken-page1-regspace"}, > > { 0, NULL}, > > }; > > > > +static inline unsigned long page1_offset_adjust( > > + unsigned long off, struct arm_smmu_device *smmu) > > +{ > > + if (off > SZ_64K && ARM_SMMU_PAGE0_REGS_ONLY(smmu)) > > + return (off - SZ_64K); > > + > > + return off; > > +} > > + > > static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) > > { > > return container_of(dom, struct arm_smmu_domain, domain); > > @@ -1986,8 +2000,10 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) > > return ret; > > > > /* evtq */ > > - ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, ARM_SMMU_EVTQ_PROD, > > - ARM_SMMU_EVTQ_CONS, EVTQ_ENT_DWORDS); > > + ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, > > + ARM_SMMU_EVTQ_PROD(smmu), > > + ARM_SMMU_EVTQ_CONS(smmu), > > + EVTQ_ENT_DWORDS); > > ...or these callsites; you can just use page1_offset_adjust() directly > within arm_smmu_init_one_queue(), i.e. > > > q->prod_reg = smmu->base + page1_offset_adjust(prod_off, smmu); > q->cons_reg = smmu->base + page1_offset_adjust(cons_off, smmu); > > because it won't affect page 0 offsets either way. > > > if (ret) > > return ret; > > > > @@ -1995,8 +2011,10 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) > > if (!(smmu->features & ARM_SMMU_FEAT_PRI)) > > return 0; > > > > - return arm_smmu_init_one_queue(smmu, &smmu->priq.q, ARM_SMMU_PRIQ_PROD, > > - ARM_SMMU_PRIQ_CONS, PRIQ_ENT_DWORDS); > > + return arm_smmu_init_one_queue(smmu, &smmu->priq.q, > > + ARM_SMMU_PRIQ_PROD(smmu), > > + ARM_SMMU_PRIQ_CONS(smmu), > > + PRIQ_ENT_DWORDS); > > } > > > > static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu) > > @@ -2363,8 +2381,10 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass) > > > > /* Event queue */ > > writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); > > - writel_relaxed(smmu->evtq.q.prod, smmu->base + ARM_SMMU_EVTQ_PROD); > > - writel_relaxed(smmu->evtq.q.cons, smmu->base + ARM_SMMU_EVTQ_CONS); > > + writel_relaxed(smmu->evtq.q.prod, smmu->base + > > + ARM_SMMU_EVTQ_PROD(smmu)); > > And correspondingly just use page1_offset_adjust(ARM_SMMU_EVTQ_*, smmu) > explicitly for these writes. > > In fact, if all the potential callsites are immediately converting the > offset into an address, then it may be worth just factoring that into > the helper as well, something like: > > static inline void __iomem *arm_smmu_page1_fixup(unsigned long offset, > struct arm_smmu_device *smmu) > { > if (offset > SZ_64K && ARM_SMMU_PAGE0_REGS_ONLY(smmu)) > offset -= SZ_64K; > > return smmu->base + offset; > } > > What do you reckon? > Just had a opinion that, replacing all page1 offset macros(ARM_SMMU_EVTQ/PRIQ_PROD/CONS) with page1_offset_adjust(ARM_SMMU_EVTQ/PRIQ_PROD/CONS, smmu) will make the changes more uniform. In that case, we wont need, offset > SZ_64K check as well. Hope the intention is not to change the offset definitions. -- Linu cherian