From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761408AbdEVTZA (ORCPT ); Mon, 22 May 2017 15:25:00 -0400 Received: from merlin.infradead.org ([205.233.59.134]:58814 "EHLO merlin.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753157AbdEVTY4 (ORCPT ); Mon, 22 May 2017 15:24:56 -0400 Date: Mon, 22 May 2017 21:24:45 +0200 From: Peter Zijlstra To: "Liang, Kan" Cc: "mingo@redhat.com" , "eranian@google.com" , "linux-kernel@vger.kernel.org" , "alexander.shishkin@linux.intel.com" , "acme@redhat.com" , "jolsa@redhat.com" , "torvalds@linux-foundation.org" , "tglx@linutronix.de" , "vincent.weaver@maine.edu" , "ak@linux.intel.com" Subject: Re: [PATCH 2/2] perf/x86/intel, watchdog: Switch NMI watchdog to ref cycles on x86 Message-ID: <20170522192445.wnkgcxc5d27mt2dz@hirez.programming.kicks-ass.net> References: <1495213582-3635-1-git-send-email-kan.liang@intel.com> <1495213582-3635-2-git-send-email-kan.liang@intel.com> <20170522120321.e3b7my5lsjue6jpb@hirez.programming.kicks-ass.net> <37D7C6CF3E00A74B8858931C1DB2F077536F07AC@SHSMSX103.ccr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <37D7C6CF3E00A74B8858931C1DB2F077536F07AC@SHSMSX103.ccr.corp.intel.com> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 22, 2017 at 04:58:04PM +0000, Liang, Kan wrote: > > > > On Fri, May 19, 2017 at 10:06:22AM -0700, kan.liang@intel.com wrote: > > > This patch was once merged, but reverted later. > > > Because ref-cycles can not be used anymore when watchdog is enabled. > > > The commit is 44530d588e142a96cf0cd345a7cb8911c4f88720 > > > > > > The patch 1/2 has extended the ref-cycles to GP counter. The concern > > > should be gone. > > > > So its not a problem if every Atom prior to Goldmont, and all Core/Core2 > > products regress? > > > > P6 and P4 you've entirely broken, as they don't have REF_CPU_CYCLES at all. > > > > So no, I don't think this is right even now. > > > > Right, the patch 1/2 doesn't cover all platforms. > I will only apply the patch for the platforms, > which have ref cycles on GP counters. Right, so if you move the weak function into arch/x86/events/core.c and simply test for x86_pmu.this_ref_alis_function_thing being !NULL that should all work.