From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755306AbdFWUZv (ORCPT ); Fri, 23 Jun 2017 16:25:51 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:34659 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755277AbdFWUZr (ORCPT ); Fri, 23 Jun 2017 16:25:47 -0400 From: Palmer Dabbelt To: corbet@lwn.net To: linux-doc@vger.kernel.org To: linux-kernel@vger.kernel.org Cc: Palmer Dabbelt Subject: [PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst Date: Fri, 23 Jun 2017 13:25:22 -0700 Message-Id: <20170623202522.6681-1-palmer@dabbelt.com> X-Mailer: git-send-email 2.13.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org I was reading the memory barries documentation in order to make sure the RISC-V barries were correct, and I found a broken link to the atomic operations documentation. Signed-off-by: Palmer Dabbelt Acked-by: Will Deacon --- Documentation/memory-barriers.txt | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index 732f10ea382e..f1c9eaa45a57 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -498,11 +498,11 @@ And a couple of implicit varieties: This means that ACQUIRE acts as a minimal "acquire" operation and RELEASE acts as a minimal "release" operation. -A subset of the atomic operations described in atomic_ops.txt have ACQUIRE -and RELEASE variants in addition to fully-ordered and relaxed (no barrier -semantics) definitions. For compound atomics performing both a load and a -store, ACQUIRE semantics apply only to the load and RELEASE semantics apply -only to the store portion of the operation. +A subset of the atomic operations described in core-api/atomic_ops.rst have +ACQUIRE and RELEASE variants in addition to fully-ordered and relaxed (no +barrier semantics) definitions. For compound atomics performing both a load +and a store, ACQUIRE semantics apply only to the load and RELEASE semantics +apply only to the store portion of the operation. Memory barriers are only required where there's a possibility of interaction between two CPUs or between a CPU and a device. If it can be guaranteed that -- 2.13.0