From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755095AbdFWUpg (ORCPT ); Fri, 23 Jun 2017 16:45:36 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:46056 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754955AbdFWUpe (ORCPT ); Fri, 23 Jun 2017 16:45:34 -0400 Date: Fri, 23 Jun 2017 13:45:29 -0700 From: "Paul E. McKenney" To: Palmer Dabbelt Cc: corbet@lwn.net, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst Reply-To: paulmck@linux.vnet.ibm.com References: <20170623203139.7258-1-palmer@dabbelt.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170623203139.7258-1-palmer@dabbelt.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 x-cbid: 17062320-0036-0000-0000-00000235137F X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007279; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000214; SDB=6.00878879; UDB=6.00437974; IPR=6.00659031; BA=6.00005438; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00015946; XFM=3.00000015; UTC=2017-06-23 20:45:32 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17062320-0037-0000-0000-000040D790AF Message-Id: <20170623204529.GO3721@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-06-23_13:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1706230349 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jun 23, 2017 at 01:31:39PM -0700, Palmer Dabbelt wrote: > I was reading the memory barries documentation in order to make sure the > RISC-V barries were correct, and I found a broken link to the atomic > operations documentation. > > Signed-off-by: Palmer Dabbelt > Acked-by: Will Deacon Good catch! Acked-by: Paul E. McKenney > --- > Documentation/memory-barriers.txt | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt > index 732f10ea382e..f1c9eaa45a57 100644 > --- a/Documentation/memory-barriers.txt > +++ b/Documentation/memory-barriers.txt > @@ -498,11 +498,11 @@ And a couple of implicit varieties: > This means that ACQUIRE acts as a minimal "acquire" operation and > RELEASE acts as a minimal "release" operation. > > -A subset of the atomic operations described in atomic_ops.txt have ACQUIRE > -and RELEASE variants in addition to fully-ordered and relaxed (no barrier > -semantics) definitions. For compound atomics performing both a load and a > -store, ACQUIRE semantics apply only to the load and RELEASE semantics apply > -only to the store portion of the operation. > +A subset of the atomic operations described in core-api/atomic_ops.rst have > +ACQUIRE and RELEASE variants in addition to fully-ordered and relaxed (no > +barrier semantics) definitions. For compound atomics performing both a load > +and a store, ACQUIRE semantics apply only to the load and RELEASE semantics > +apply only to the store portion of the operation. > > Memory barriers are only required where there's a possibility of interaction > between two CPUs or between a CPU and a device. If it can be guaranteed that > -- > 2.13.0 >