From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751998AbdF1QI1 (ORCPT ); Wed, 28 Jun 2017 12:08:27 -0400 Received: from mga05.intel.com ([192.55.52.43]:12452 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751541AbdF1QIS (ORCPT ); Wed, 28 Jun 2017 12:08:18 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,276,1496127600"; d="scan'208";a="102357129" Date: Wed, 28 Jun 2017 09:09:52 -0700 From: Jacob Pan To: Joerg Roedel Cc: iommu@lists.linux-foundation.org, LKML , David Woodhouse , "Liu, Yi L" , Lan Tianyu , "Tian, Kevin" , Raj Ashok , Alex Williamson , Jean Delvare , "Liu, Yi L" , jacob.jun.pan@linux.intel.com Subject: Re: [PATCH 3/9] iommu: Introduce iommu do invalidate API function Message-ID: <20170628090952.0bebd2b3@jacob-builder> In-Reply-To: <20170628100823.GG14532@8bytes.org> References: <1498592883-56224-1-git-send-email-jacob.jun.pan@linux.intel.com> <1498592883-56224-4-git-send-email-jacob.jun.pan@linux.intel.com> <20170628100823.GG14532@8bytes.org> Organization: OTC X-Mailer: Claws Mail 3.13.2 (GTK+ 2.24.30; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 28 Jun 2017 12:08:23 +0200 Joerg Roedel wrote: > On Tue, Jun 27, 2017 at 12:47:57PM -0700, Jacob Pan wrote: > > From: "Liu, Yi L" > > > > When a SVM capable device is assigned to a guest, the first level > > page tables are owned by the guest and the guest PASID table > > pointer is linked to the device context entry of the physical IOMMU. > > > > Host IOMMU driver has no knowledge of caching structure updates > > unless the guest invalidation activities are passed down to the > > host. The primary usage is derived from emulated IOMMU in the > > guest, where QEMU can trap invalidation activities before pass them > > down the host/physical IOMMU. There are IOMMU architectural > > specific actions need to be taken which requires the generic APIs > > introduced in this patch to have opaque data in the > > tlb_invalidate_info argument. > > Which "IOMMU architectural specific actions" are you thinking of? > construction of queued invalidation descriptors, then submit them to the IOMMU QI interface. > > +int iommu_invalidate(struct iommu_domain *domain, > > + struct device *dev, struct tlb_invalidate_info > > *inv_info) +{ > > + int ret = 0; > > + > > + if (unlikely(!domain->ops->invalidate)) > > + return -ENODEV; > > + > > + ret = domain->ops->invalidate(domain, dev, inv_info); > > + > > + return ret; > > +} > > +EXPORT_SYMBOL_GPL(iommu_invalidate); > > [...] > > > +struct tlb_invalidate_info { > > + __u32 model; > > + __u32 length; > > + __u8 opaque[]; > > +}; > > This interface is aweful. It requires the user of a generic api to > know details about the implementation behind to do anything useful. > > Please explain in more detail why this is needed. My feeling is that > we can make this more generic with a small set of invalidation > functions in the iommu-api. > My thinking was that via configuration control, there will be unlikely any mixed IOMMU models between pIOMMU and vIOMMU. We could have just model specific data pass through layers of SW (QEMU, VFIO) for performance reasons. We do have an earlier hybrid version that has generic data and opaque raw data. Would the below work for all IOMMU models? https://www.spinics.net/lists/kvm/msg148798.html struct tlb_invalidate_info { __u32 model; /* Vendor number */ __u8 granularity #define DEVICE_SELECTVIE_INV (1 << 0) #define PAGE_SELECTIVE_INV (1 << 0) #define PASID_SELECTIVE_INV (1 << 1) __u32 pasid; __u64 addr; __u64 size; /* Since IOMMU format has already been validated for this table, the IOMMU driver knows that the following structure is in a format it knows */ __u8 opaque[]; }; > > > Joerg > [Jacob Pan]