From: Marc Zyngier <marc.zyngier@arm.com>
To: linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu
Cc: Christoffer Dall <christoffer.dall@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Eric Auger <eric.auger@redhat.com>,
Shanker Donthineni <shankerd@codeaurora.org>,
Mark Rutland <mark.rutland@arm.com>
Subject: [PATCH v2 06/52] irqchip/gic-v3-its: Macro-ize its_send_single_command
Date: Wed, 28 Jun 2017 16:03:25 +0100 [thread overview]
Message-ID: <20170628150411.15846-7-marc.zyngier@arm.com> (raw)
In-Reply-To: <20170628150411.15846-1-marc.zyngier@arm.com>
Most ITS commands do operate on a collection object, and require
a SYNC command to be performed on that collection in order to
guarantee the execution of the first command.
With GICv4 ITS, another set of commands perform similar operations
on a VPE object, and a VSYNC operations must be executed to guarantee
their execution.
Given the similarities (post a command, perform a synchronization
operation on a sync object), it makes sense to reuse the same
mechanism for both class of commands.
Let's start with turning its_send_single_command into a huge macro
that performs the bulk of the work, and a set of helpers that
make this macro usable for the GICv3 ITS commands.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
drivers/irqchip/irq-gic-v3-its.c | 84 ++++++++++++++++++++++------------------
1 file changed, 47 insertions(+), 37 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 006a5259609d..bbf7bb89aa62 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -490,43 +490,53 @@ static void its_wait_for_range_completion(struct its_node *its,
}
}
-static void its_send_single_command(struct its_node *its,
- its_cmd_builder_t builder,
- struct its_cmd_desc *desc)
-{
- struct its_cmd_block *cmd, *sync_cmd, *next_cmd;
- struct its_collection *sync_col;
- unsigned long flags;
-
- raw_spin_lock_irqsave(&its->lock, flags);
-
- cmd = its_allocate_entry(its);
- if (!cmd) { /* We're soooooo screewed... */
- pr_err_ratelimited("ITS can't allocate, dropping command\n");
- raw_spin_unlock_irqrestore(&its->lock, flags);
- return;
- }
- sync_col = builder(cmd, desc);
- its_flush_cmd(its, cmd);
-
- if (sync_col) {
- sync_cmd = its_allocate_entry(its);
- if (!sync_cmd) {
- pr_err_ratelimited("ITS can't SYNC, skipping\n");
- goto post;
- }
- its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
- its_encode_target(sync_cmd, sync_col->target_address);
- its_fixup_cmd(sync_cmd);
- its_flush_cmd(its, sync_cmd);
- }
-
-post:
- next_cmd = its_post_commands(its);
- raw_spin_unlock_irqrestore(&its->lock, flags);
-
- its_wait_for_range_completion(its, cmd, next_cmd);
-}
+/* Warning, macro hell follows */
+#define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \
+void name(struct its_node *its, \
+ buildtype builder, \
+ struct its_cmd_desc *desc) \
+{ \
+ struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \
+ synctype *sync_obj; \
+ unsigned long flags; \
+ \
+ raw_spin_lock_irqsave(&its->lock, flags); \
+ \
+ cmd = its_allocate_entry(its); \
+ if (!cmd) { /* We're soooooo screewed... */ \
+ raw_spin_unlock_irqrestore(&its->lock, flags); \
+ return; \
+ } \
+ sync_obj = builder(cmd, desc); \
+ its_flush_cmd(its, cmd); \
+ \
+ if (sync_obj) { \
+ sync_cmd = its_allocate_entry(its); \
+ if (!sync_cmd) \
+ goto post; \
+ \
+ buildfn(sync_cmd, sync_obj); \
+ its_flush_cmd(its, sync_cmd); \
+ } \
+ \
+post: \
+ next_cmd = its_post_commands(its); \
+ raw_spin_unlock_irqrestore(&its->lock, flags); \
+ \
+ its_wait_for_range_completion(its, cmd, next_cmd); \
+}
+
+static void its_build_sync_cmd(struct its_cmd_block *sync_cmd,
+ struct its_collection *sync_col)
+{
+ its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
+ its_encode_target(sync_cmd, sync_col->target_address);
+
+ its_fixup_cmd(sync_cmd);
+}
+
+static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
+ struct its_collection, its_build_sync_cmd)
static void its_send_inv(struct its_device *dev, u32 event_id)
{
--
2.11.0
next prev parent reply other threads:[~2017-06-28 15:20 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-28 15:03 [PATCH v2 00/52] irqchip: KVM: Add support for GICv4 Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 01/52] genirq: Let irq_set_vcpu_affinity() iterate over hierarchy Marc Zyngier
2017-07-04 21:15 ` Thomas Gleixner
2017-06-28 15:03 ` [PATCH v2 02/52] irqchip/gic-v3: Add redistributor iterator Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 03/52] irqchip/gic-v3: Add VLPI/DirectLPI discovery Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 04/52] irqchip/gic-v3-its: Move LPI definitions around Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 05/52] irqchip/gic-v3-its: Add probing for VLPI properties Marc Zyngier
2017-06-28 15:03 ` Marc Zyngier [this message]
2017-06-28 15:03 ` [PATCH v2 07/52] irqchip/gic-v3-its: Implement irq_set_irqchip_state for pending state Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 08/52] irqchip/gic-v3-its: Split out property table allocation Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 09/52] irqchip/gic-v3-its: Allow use of indirect VCPU tables Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 10/52] irqchip/gic-v3-its: Split out pending table allocation Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 11/52] irqchip/gic-v3-its: Rework LPI freeing Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 12/52] irqchip/gic-v3-its: Generalize device table allocation Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 13/52] irqchip/gic-v3-its: Generalize LPI configuration Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 14/52] irqchip/gic-v4: Add management structure definitions Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 15/52] irqchip/gic-v3-its: Add GICv4 ITS command definitions Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 16/52] irqchip/gic-v3-its: Add VLPI configuration hook Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 17/52] irqchip/gic-v3-its: Add VLPI map/unmap operations Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 18/52] irqchip/gic-v3-its: Add VLPI configuration handling Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 19/52] irqchip/gic-v3-its: Add VPE domain infrastructure Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 20/52] irqchip/gic-v3-its: Add VPE irq domain allocation/teardown Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 21/52] irqchip/gic-v3-its: Add VPE irq domain [de]activation Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 22/52] irqchip/gic-v3-its: Add VPENDBASER/VPROPBASER accessors Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 23/52] irqchip/gic-v3-its: Add VPE scheduling Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 24/52] irqchip/gic-v3-its: Add VPE invalidation hook Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 25/52] irqchip/gic-v3-its: Add VPE affinity changes Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 26/52] irqchip/gic-v3-its: Add VPE interrupt masking Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 27/52] irqchip/gic-v3-its: Support VPE doorbell invalidation even when !DirectLPI Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 28/52] irqchip/gic-v3-its: Set implementation defined bit to enable VLPIs Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 29/52] irqchip/gic-v4: Add per-VM VPE domain creation Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 30/52] irqchip/gic-v4: Add VPE command interface Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 31/52] irqchip/gic-v4: Add VLPI configuration interface Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 32/52] irqchip/gic-v4: Add some basic documentation Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 33/52] irqchip/gic-v4: Enable low-level GICv4 operations Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 34/52] irqchip/gic-v3: Advertise GICv4 support to KVM Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 35/52] KVM: arm/arm64: vgic: Move kvm_vgic_destroy call around Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 36/52] KVM: arm/arm64: vITS: Add MSI translation helpers Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 37/52] KVM: arm/arm64: GICv4: Add init and teardown of the vPE irq domain Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 38/52] KVM: arm/arm64: GICv4: Wire init/teardown of per-VM support Marc Zyngier
2017-07-08 11:26 ` Shanker Donthineni
2017-07-10 16:34 ` Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 39/52] KVM: arm/arm64: GICv4: Wire mapping/unmapping of VLPIs in VFIO irq bypass Marc Zyngier
2017-06-28 15:03 ` [PATCH v2 40/52] KVM: arm/arm64: GICv4: Handle INT command applied to a VLPI Marc Zyngier
2017-06-28 15:04 ` [PATCH v2 41/52] KVM: arm/arm64: GICv4: Unmap VLPI when freeing an LPI Marc Zyngier
2017-06-28 15:04 ` [PATCH v2 42/52] KVM: arm/arm64: GICv4: Handle MOVI applied to a VLPI Marc Zyngier
2017-06-28 15:04 ` [PATCH v2 43/52] KVM: arm/arm64: GICv4: Handle CLEAR " Marc Zyngier
2017-06-28 15:04 ` [PATCH v2 44/52] KVM: arm/arm64: GICv4: Handle MOVALL applied to a vPE Marc Zyngier
2017-06-28 15:04 ` [PATCH v2 45/52] KVM: arm/arm64: GICv4: Propagate property updates to VLPIs Marc Zyngier
2017-06-28 15:04 ` [PATCH v2 46/52] KVM: arm/arm64: GICv4: Handle INVALL applied to a vPE Marc Zyngier
2017-06-28 15:04 ` [PATCH v2 47/52] KVM: arm/arm64: GICv4: Propagate VLPI properties at map time Marc Zyngier
2017-06-28 15:04 ` [PATCH v2 48/52] KVM: arm/arm64: GICv4: Add doorbell interrupt handling Marc Zyngier
2017-06-28 15:04 ` [PATCH v2 49/52] KVM: arm/arm64: GICv4: Hook vPE scheduling into vgic flush/sync Marc Zyngier
2017-06-28 15:04 ` [PATCH v2 50/52] KVM: arm/arm64: GICv4: Enable virtual cpuif if VLPIs can be delivered Marc Zyngier
2017-06-28 15:04 ` [PATCH v2 51/52] KVM: arm/arm64: GICv4: Use pending_last as a scheduling hint Marc Zyngier
2017-06-28 15:04 ` [PATCH v2 52/52] KVM: arm/arm64: GICv4: Enable VLPI support Marc Zyngier
2017-07-01 14:54 ` [PATCH v2 00/52] irqchip: KVM: Add support for GICv4 Shanker Donthineni
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20170628150411.15846-7-marc.zyngier@arm.com \
--to=marc.zyngier@arm.com \
--cc=christoffer.dall@linaro.org \
--cc=eric.auger@redhat.com \
--cc=jason@lakedaemon.net \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=shankerd@codeaurora.org \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).