From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
To: Linus Torvalds <torvalds@linux-foundation.org>,
Andrew Morton <akpm@linux-foundation.org>,
x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>
Cc: Andi Kleen <ak@linux.intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Andy Lutomirski <luto@amacapital.net>,
linux-arch@vger.kernel.org, linux-mm@kvack.org,
linux-kernel@vger.kernel.org,
"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Subject: [PATCH 3/8] x86/xen: Redefine XEN_ELFNOTE_INIT_P2M using PUD_SIZE * PTRS_PER_PUD
Date: Mon, 17 Jul 2017 01:59:49 +0300 [thread overview]
Message-ID: <20170716225954.74185-4-kirill.shutemov@linux.intel.com> (raw)
In-Reply-To: <20170716225954.74185-1-kirill.shutemov@linux.intel.com>
XEN_ELFNOTE_INIT_P2M has to be 512GB for both 4- and 5-level paging.
(PUD_SIZE * PTRS_PER_PUD) would do this.
Unfortunately, we cannot use P4D_SIZE, which would fit here. With
current headers structure it cannot be used in assembly, if p4d
level is folded.
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
---
arch/x86/xen/xen-head.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/xen/xen-head.S b/arch/x86/xen/xen-head.S
index 72a8e6adebe6..a7525e95d53f 100644
--- a/arch/x86/xen/xen-head.S
+++ b/arch/x86/xen/xen-head.S
@@ -58,7 +58,7 @@ ENTRY(hypercall_page)
#else
ELFNOTE(Xen, XEN_ELFNOTE_VIRT_BASE, _ASM_PTR __START_KERNEL_map)
/* Map the p2m table to a 512GB-aligned user address. */
- ELFNOTE(Xen, XEN_ELFNOTE_INIT_P2M, .quad PGDIR_SIZE)
+ ELFNOTE(Xen, XEN_ELFNOTE_INIT_P2M, .quad (PUD_SIZE * PTRS_PER_PUD))
#endif
#ifdef CONFIG_XEN_PV
ELFNOTE(Xen, XEN_ELFNOTE_ENTRY, _ASM_PTR startup_xen)
--
2.11.0
next prev parent reply other threads:[~2017-07-16 23:00 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-16 22:59 [PATCH 0/8] 5-level paging enabling for v4.14 Kirill A. Shutemov
2017-07-16 22:59 ` [PATCH 1/8] x86/dump_pagetables: Generalize address normalization Kirill A. Shutemov
2017-07-21 9:38 ` [tip:x86/mm] x86/mm/dump_pagetables: " tip-bot for Kirill A. Shutemov
2017-07-16 22:59 ` [PATCH 2/8] x86/dump_pagetables: Fix printout of p4d level Kirill A. Shutemov
2017-07-21 9:38 ` [tip:x86/mm] x86/mm/dump_pagetables: " tip-bot for Kirill A. Shutemov
2017-07-16 22:59 ` Kirill A. Shutemov [this message]
2017-07-17 5:45 ` [PATCH 3/8] x86/xen: Redefine XEN_ELFNOTE_INIT_P2M using PUD_SIZE * PTRS_PER_PUD Juergen Gross
2017-07-21 9:39 ` [tip:x86/mm] " tip-bot for Kirill A. Shutemov
2017-07-16 22:59 ` [PATCH 4/8] x86/mm: Rename tasksize_32bit/64bit to task_size_32bit/64bit Kirill A. Shutemov
2017-07-21 9:39 ` [tip:x86/mm] x86/mm: Rename tasksize_32bit/64bit to task_size_32bit/64bit() tip-bot for Kirill A. Shutemov
2017-07-16 22:59 ` [PATCH 5/8] x86/mpx: Do not allow MPX if we have mappings above 47-bit Kirill A. Shutemov
2017-07-21 9:40 ` [tip:x86/mm] " tip-bot for Kirill A. Shutemov
2017-07-16 22:59 ` [PATCH 6/8] x86/mm: Prepare to expose larger address space to userspace Kirill A. Shutemov
2017-07-21 9:40 ` [tip:x86/mm] " tip-bot for Kirill A. Shutemov
2017-07-16 22:59 ` [PATCH 7/8] x86/mm: Allow userspace have mapping above 47-bit Kirill A. Shutemov
2017-07-21 9:40 ` [tip:x86/mm] x86/mm: Allow userspace have mappings " tip-bot for Kirill A. Shutemov
2017-07-16 22:59 ` [PATCH 8/8] x86: Enable 5-level paging support Kirill A. Shutemov
2017-07-21 9:41 ` [tip:x86/mm] x86: Enable 5-level paging support via CONFIG_X86_5LEVEL=y tip-bot for Kirill A. Shutemov
2017-07-20 7:57 ` [PATCH 0/8] 5-level paging enabling for v4.14 Kirill A. Shutemov
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