From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751320AbdGQFTb (ORCPT ); Mon, 17 Jul 2017 01:19:31 -0400 Received: from mx2.suse.de ([195.135.220.15]:34410 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751093AbdGQFT3 (ORCPT ); Mon, 17 Jul 2017 01:19:29 -0400 Date: Mon, 17 Jul 2017 07:19:25 +0200 From: Borislav Petkov To: Yazen Ghannam Cc: linux-edac@vger.kernel.org, Tony Luck , x86@kernel.org, linux-kernel@vger.kernel.org, jack@codezen.org Subject: Re: [PATCH] x86/mce/AMD: Allow any CPU to initialize smca_banks array Message-ID: <20170717051925.GA18200@nazgul.tnic> References: <20170628000630.1973-1-jack@codezen.org> <1498759708-27680-1-git-send-email-Yazen.Ghannam@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1498759708-27680-1-git-send-email-Yazen.Ghannam@amd.com> User-Agent: Mutt/1.6.0 (2016-04-01) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jun 29, 2017 at 01:08:28PM -0500, Yazen Ghannam wrote: > From: Yazen Ghannam > > Current SMCA implementations have the same banks on each CPU with the > non-core banks only visible to a "master thread" on each Die. Practically, > this means the smca_banks array, which describes the banks, only needs to > be populated once by a single master thread. ... > If the first CPU up is not a master thread, then it will populate the array > with all core banks. The first CPU afterwards that is a master thread will > skip populating the core banks and continue populating the non-core banks. > Every CPU afterwards will then return early. > > Signed-off-by: Yazen Ghannam > --- > arch/x86/kernel/cpu/mcheck/mce_amd.c | 9 ++------- > 1 file changed, 2 insertions(+), 7 deletions(-) Applied, thanks. -- Regards/Gruss, Boris. SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg) --