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Date: Fri, 21 Jul 2017 09:19:48 +0200
From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Chen-Yu Tsai <wens@csie.org>
Cc: Ulf Hansson <ulf.hansson@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@codeaurora.org>, Rob Herring <robh+dt@kernel.org>,
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        linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com
Subject: Re: [PATCH v2 02/10] clk: sunxi-ng: Add MP_MMC clocks that support
 MMC timing modes switching
Message-ID: <20170721071948.jofji4lwbq6s4ims@flea>
References: <20170720034452.15920-1-wens@csie.org>
 <20170720034452.15920-3-wens@csie.org>
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On Thu, Jul 20, 2017 at 11:44:44AM +0800, Chen-Yu Tsai wrote:
> +/* Special class of M-P clock that supports MMC timing modes */
> +
> +#define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg,	\
> +				       _mshift, _mwidth,		\
> +				       _pshift, _pwidth,		\
> +				       _muxshift, _muxwidth,		\
> +				       _gate, _flags)			\
> +	struct ccu_mp _struct =3D {					\
> +		.enable	=3D _gate,					\
> +		.m	=3D _SUNXI_CCU_DIV(_mshift, _mwidth),		\
> +		.p	=3D _SUNXI_CCU_DIV(_pshift, _pwidth),		\
> +		.mux	=3D _SUNXI_CCU_MUX(_muxshift, _muxwidth),		\
> +		.common	=3D {						\
> +			.reg		=3D _reg,				\
> +			.features	=3D CCU_FEATURE_MMC_TIMING_SWITCH, \
> +			.hw.init	=3D CLK_HW_INIT_PARENTS(_name,	\
> +							      _parents, \
> +							      &ccu_mp_mmc_ops, \
> +							      _flags),	\
> +		}							\
> +	}
> +
> +extern const struct clk_ops ccu_mp_mmc_ops;
> +

I guess we can simplify a lot that macro, all the new-timings MMC
clocks have the same register layout.

Maxime

--=20
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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