From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752001AbdHGBrC (ORCPT ); Sun, 6 Aug 2017 21:47:02 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:49937 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751748AbdHGBqw (ORCPT ); Sun, 6 Aug 2017 21:46:52 -0400 From: Chris Packham To: robh+dt@kernel.org, gregory.clement@free-electrons.com, bp@alien8.de, jlu@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Chris Packham , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Mark Rutland , Russell King , devicetree@vger.kernel.org Subject: [RESEND PATCH 3/4] ARM: dts: mvebu: set reduced-width property for SDRAM on 98dx3236 Date: Mon, 7 Aug 2017 13:46:40 +1200 Message-Id: <20170807014641.4003-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170807014641.4003-1-chris.packham@alliedtelesis.co.nz> References: <20170807014641.4003-1-chris.packham@alliedtelesis.co.nz> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Because the 98dx3236 and similar SoCs are switch chips with integrated CPUs they use a reduced pin count for the SDRAM interface. As such "full" with is 32-bits and "half" width is 16-bits (as opposed to 64/32 on the discrete SoC). Set the reduced-width property on the sdramc node to indicate this. Signed-off-by: Chris Packham --- arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi index 0e12816d961e..4d6a2acc1b55 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -129,6 +129,7 @@ sdramc@1400 { compatible = "marvell,armada-xp-sdram-controller"; reg = <0x1400 0x500>; + marvell,reduced-width; }; L2: l2-cache@8000 { -- 2.13.0