From: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
To: Julia Cartwright <julia@ni.com>
Cc: Haris Okanovic <haris.okanovic@ni.com>,
linux-rt-users@vger.kernel.org, linux-kernel@vger.kernel.org,
harisokn@gmail.com, gratian.crisan@ni.com, scott.hartman@ni.com,
chris.graf@ni.com, brad.mouring@ni.com, jonathan.david@ni.com
Subject: Re: [PATCH] [RFC] tpm_tis: tpm_tcg_flush() after iowrite*()s
Date: Wed, 9 Aug 2017 00:58:48 +0300 [thread overview]
Message-ID: <20170808215848.nngnph6wkqvx6zh3@linux.intel.com> (raw)
In-Reply-To: <20170807145935.GW8384@jcartwri.amer.corp.natinst.com>
On Mon, Aug 07, 2017 at 09:59:35AM -0500, Julia Cartwright wrote:
> On Fri, Aug 04, 2017 at 04:56:51PM -0500, Haris Okanovic wrote:
> > I have a latency issue using a SPI-based TPM chip with tpm_tis driver
> > from non-rt usermode application, which induces ~400 us latency spikes
> > in cyclictest (Intel Atom E3940 system, PREEMPT_RT_FULL kernel).
> >
> > The spikes are caused by a stalling ioread8() operation, following a
> > sequence of 30+ iowrite8()s to the same address. I believe this happens
> > because the writes are cached (in cpu or somewhere along the bus), which
> > gets flushed on the first LOAD instruction (ioread*()) that follows.
>
> To use the ARM parlance, these accesses aren't "cached" (which would
> imply that a result could be returned to the load from any intermediate
> node in the interconnect), but instead are "bufferable".
>
> It is really unfortunate that we continue to run into this class of
> problem across various CPU vendors and various underlying bus
> technologies; it's the continuing curse of running an PREEMPT_RT on
> commodity hardware. RT is not easy :)
>
> > The enclosed change appears to fix this issue: read the TPM chip's
> > access register (status code) after every iowrite*() operation.
>
> Are we engaged in a game of wack-a-mole with all of the drivers which
> use this same access pattern (of which I imagine there are quite a
> few!)?
>
> I'm wondering if we should explore the idea of adding a load in the
> iowriteN()/writeX() macros (marking those accesses in which reads cause
> side effects explicitly, redirecting to a _raw() variant or something).
>
> Obviously that would be expensive for non-RT use cases, but for helping
> constrain latency, it may be worth it for RT.
>
> Julia
What if we as quick resort we add tpm_tis_iowrite8() to the TPM driver.
Would be easy to move to iowrite8() if the problem is sorted out there
later on.
/Jarkko
next prev parent reply other threads:[~2017-08-08 21:58 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-04 21:56 [PATCH] [RFC] tpm_tis: tpm_tcg_flush() after iowrite*()s Haris Okanovic
2017-08-07 14:59 ` Julia Cartwright
2017-08-08 21:58 ` Jarkko Sakkinen [this message]
2017-08-14 22:53 ` Haris Okanovic
2017-08-14 22:52 ` Haris Okanovic
2017-08-14 22:53 ` [PATCH] tpm_tis: fix stall " Haris Okanovic
2017-08-15 6:11 ` Alexander Stein
2017-08-15 20:10 ` Haris Okanovic
2017-08-15 20:13 ` [PATCH v2] " Haris Okanovic
2017-08-16 21:15 ` [tpmdd-devel] " Ken Goldman
2017-08-17 5:57 ` Alexander Stein
2017-08-17 10:38 ` Sebastian Andrzej Siewior
2017-08-17 17:17 ` Jason Gunthorpe
2017-08-17 20:12 ` Haris Okanovic
2017-08-19 17:03 ` Jarkko Sakkinen
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