From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751969AbdHQD5L (ORCPT ); Wed, 16 Aug 2017 23:57:11 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:4017 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751549AbdHQD5J (ORCPT ); Wed, 16 Aug 2017 23:57:09 -0400 Date: Thu, 17 Aug 2017 04:56:22 +0100 From: Jonathan Cameron To: Zhangshaokun CC: Mark Rutland , , , , , Subject: Re: [PATCH v4 1/6] Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver Message-ID: <20170817045622.00000669@huawei.com> In-Reply-To: References: <1500984642-204676-1-git-send-email-zhangshaokun@hisilicon.com> <1500984642-204676-2-git-send-email-zhangshaokun@hisilicon.com> <20170815095005.GB6090@leverpostej> Organization: Huawei X-Mailer: Claws Mail 3.15.0 (GTK+ 2.24.31; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.206.48.115] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.599513F8.0013,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ef1a557b03910a438f1424548951fde6 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 17 Aug 2017 10:30:23 +0800 Zhangshaokun wrote: > Hi Mark, > > Thanks for your comments. > > On 2017/8/15 17:50, Mark Rutland wrote: > > Hi, > > > > On Tue, Jul 25, 2017 at 08:10:37PM +0800, Shaokun Zhang wrote: > >> This patch adds documentation for the uncore PMUs on HiSilicon SoC. > >> > >> Reviewed-by: Jonathan Cameron > >> Signed-off-by: Shaokun Zhang > >> Signed-off-by: Anurup M > >> --- > >> Documentation/perf/hisi-pmu.txt | 52 +++++++++++++++++++++++++++++++++++++++++ > >> 1 file changed, 52 insertions(+) > >> create mode 100644 Documentation/perf/hisi-pmu.txt > >> > >> diff --git a/Documentation/perf/hisi-pmu.txt b/Documentation/perf/hisi-pmu.txt > >> new file mode 100644 > >> index 0000000..f45a03d > >> --- /dev/null > >> +++ b/Documentation/perf/hisi-pmu.txt > >> @@ -0,0 +1,52 @@ > >> +HiSilicon SoC uncore Performance Monitoring Unit (PMU) > >> +====================================================== > >> +The HiSilicon SoC chip comprehends various independent system device PMUs > > > > Nit: s/comprehends/comprises/ would be easier to read. > > > > Ok. s/comprises/includes/ would perhaps be even better. There are a few other things in the SoC beyond independent system device PMUs :) (good spot though - I completely missed comprehends when doing the internal review!) > > >> +such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are > >> +independent and have hardware logic to gather statistics and performance > >> +information. > >> + > >> +HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster > > > > Nit: The Hisilicon SoC > > > > Ok. I disagree. It is odd but the company name is HiSilicon with the capital S. > > >> +(CCL) is made up of 4 cpu cores sharing one L3 cache; Each CPU die is > > > > Nit: s/Each/each/ > > > > Ok. > > >> +called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has > >> +two HHAs (0 - 1) and four DDRCs (0 - 3), respectively. > >> + > >> +HiSilicon SoC uncore PMU driver > >> +--------------------------------------- > >> +Each device PMU has separate registers for event counting, control and > >> +interrupt, and the PMU driver shall register perf PMU drivers like L3C, > >> +HHA and DDRC etc. The available events and configuration options shall > >> +be described in the sysfs, see /sys/devices/hisi_* > > > > What exactly its exposed under /sys/devices/hisi_* ? > > > > Apologies that i shall list /sys/devices/hisi_sccl{X}_/ and > will change it in next version. > > >> or /sys/bus/ > >> +event_source/devices/hisi_*. > > > > Please don't wrap paths; keep this on one line. > > > > Ok. > > >> +The "perf list" command shall list the available events from sysfs. > >> + > >> +Each L3C, HHA and DDRC in one SCCL are registered as an separate PMU with perf. > >> +The PMU name will appear in event listing as hisi_module _. > >> +where "index-id" is the index of module and "sccl-id" is the identifier of > >> +the SCCL. > >> +e.g. hisi_l3c0_1/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 and SCCL > >> +ID #1. > >> +e.g. hisi_hha0_1/rx_operations is RX_OPERATIONS event of HHA index #0 and SCCL > >> +ID #1. > > > > It would make more sense for this to be hierarichal, e.g. hisi_sccl{X}_l3c{Y}. > > > > Surely, it is nicer. > > Thanks. > Shaokun > > > Other than the above nits, this documentation is very useful. Thanks for > > putting this together. > > > > Thanks, > > Mark. > > _______________________________________________ > > linuxarm mailing list > > linuxarm@huawei.com > > http://rnd-openeuler.huawei.com/mailman/listinfo/linuxarm > > > > . > > > > _______________________________________________ > linuxarm mailing list > linuxarm@huawei.com > http://rnd-openeuler.huawei.com/mailman/listinfo/linuxarm