From: Andrew Lunn <andrew@lunn.ch>
To: Fahad Kunnathadi <fahad.kunnathadi@dexceldesigns.com>
Cc: f.fainelli@gmail.com, netdev@vger.kernel.org,
michal.simek@xilinx.com, linux-kernel@vger.kernel.org,
soren.brinkmann@xilinx.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter speed register.
Date: Thu, 14 Sep 2017 16:34:54 +0200 [thread overview]
Message-ID: <20170914143454.GB27601@lunn.ch> (raw)
In-Reply-To: <1505373391-18697-1-git-send-email-fahad.kunnathadi@dexceldesigns.com>
On Thu, Sep 14, 2017 at 12:46:31PM +0530, Fahad Kunnathadi wrote:
> To clear Speed Selection in MDIO control register(0x10),
> ie, clear bits 6 and 13 to zero while keeping other bits same.
> Before AND operation,The Mask value has to be perform with bitwise NOT
> operation (ie, ~ operator)
>
> This patch clears current speed selection before writing the
> new speed settings to gmii2rgmii converter
Hi Fahad
I expect you will find other issues with this driver. I pointed some
out at the time it is submitted, but the developers went quiet as soon
as it was accepted.
Anyway, please ensure David Miller <davem@davemloft.net> gets a copy.
The subject line should be:
[PATCH net] net: phy: Fix mask value write on gmii2rgmii converter speed register.
and include a fixes tag:
Fixes: f411a6160bd4 ("net: phy: Add gmiitorgmii converter support")
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
next prev parent reply other threads:[~2017-09-14 15:01 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-14 7:16 [PATCH] net: phy: Fix mask value write on gmii2rgmii converter speed register Fahad Kunnathadi
2017-09-14 14:34 ` Andrew Lunn [this message]
2017-09-15 7:16 ` Fahad Kunnathadi
2017-09-15 7:49 ` Michal Simek
2017-09-15 14:10 ` Andrew Lunn
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