From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751628AbdINXtk (ORCPT ); Thu, 14 Sep 2017 19:49:40 -0400 Received: from muru.com ([72.249.23.125]:40744 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751550AbdINXti (ORCPT ); Thu, 14 Sep 2017 19:49:38 -0400 Date: Thu, 14 Sep 2017 16:49:35 -0700 From: Tony Lindgren To: Linus Walleij Cc: Thierry Reding , Jonathan Hunter , "linux-gpio@vger.kernel.org" , "linux-tegra@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Grygorii Strashko , linux-omap@vger.kernel.org Subject: Re: [PATCH 14/16] gpio: Add support for banked GPIO controllers Message-ID: <20170914234934.GV5024@atomide.com> References: <20170901185736.28051-1-thierry.reding@gmail.com> <20170901185736.28051-15-thierry.reding@gmail.com> <20170914233731.GU5024@atomide.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170914233731.GU5024@atomide.com> User-Agent: Mutt/1.8.3 (2017-05-23) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Tony Lindgren [170914 16:38]: > * Linus Walleij [170914 07:00]: > > On Fri, Sep 1, 2017 at 8:57 PM, Thierry Reding wrote: > > > > > From: Thierry Reding > > > > > > Some GPIO controllers are subdivided into multiple logical blocks called > > > banks (or ports). This is often caused by the design assigning separate > > > resources, such as register regions or interrupts, to each bank, or some > > > set of banks. > > > > > > This commit adds support for describing controllers that have such a > > > banked design and provides common code for dealing with them. > > > > > > Signed-off-by: Thierry Reding > > > > This patch makes me really happy. > > > > It pulls in a lot of weirdness to the OF core and creates a coherent > > way of handling these "banked" GPIO chips. > > > > CC to Tony to make sure he checks that OMAP is ready to use this > > too. > > Adding Grygorii to Cc as well, we'll take a look. > > Probably the runtime PM will be an issue here still. We must currently > do runtime PM on per GPIO bank basis instead of per GPIO pin level as > we constantly runtime_suspend/resume the whole GPIO bank for idle modes > on the SoCs that support PM. So the usage count for the bank needs to > be either 0 or 1 and cannot be the lines used in the bank. And based on a quick look at this series it should not cause problems there. For managing the banks in a generic way, I like the idea too. Regards, Tony