From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753161AbdIXUCV (ORCPT ); Sun, 24 Sep 2017 16:02:21 -0400 Received: from mail-wm0-f41.google.com ([74.125.82.41]:47323 "EHLO mail-wm0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752893AbdIXUAl (ORCPT ); Sun, 24 Sep 2017 16:00:41 -0400 X-Google-Smtp-Source: AOwi7QDv0lTIaV9z1KMm4b3kBdFyRDiKK4sqkyhsst3WY+ZakgYJIGy9jDKl3afBamRWXi7Jii7Utg== From: Jerome Brunet To: Stephen Boyd , Michael Turquette Cc: Jerome Brunet , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Russell King , Linus Walleij , Quentin Schulz , Kevin Hilman Subject: [PATCH v4 03/10] clk: add clk_core_set_phase_nolock function Date: Sun, 24 Sep 2017 22:00:23 +0200 Message-Id: <20170924200030.6227-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170924200030.6227-1-jbrunet@baylibre.com> References: <20170924200030.6227-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Create a core function for set_phase, as it is done for set_rate and set_parent. This rework is done to ease the integration of "protected" clock functionality. Acked-by: Linus Walleij Tested-by: Quentin Schulz Signed-off-by: Jerome Brunet --- drivers/clk/clk.c | 33 +++++++++++++++++++++------------ 1 file changed, 21 insertions(+), 12 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 3518f251cfd5..0913688dacb0 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1875,6 +1875,25 @@ int clk_set_parent(struct clk *clk, struct clk *parent) } EXPORT_SYMBOL_GPL(clk_set_parent); +static int clk_core_set_phase_nolock(struct clk_core *core, int degrees) +{ + int ret = -EINVAL; + + lockdep_assert_held(&prepare_lock); + + if (!core) + return 0; + + trace_clk_set_phase(core, degrees); + + if (core->ops->set_phase) + ret = core->ops->set_phase(core->hw, degrees); + + trace_clk_set_phase_complete(core, degrees); + + return ret; +} + /** * clk_set_phase - adjust the phase shift of a clock signal * @clk: clock signal source @@ -1897,7 +1916,7 @@ EXPORT_SYMBOL_GPL(clk_set_parent); */ int clk_set_phase(struct clk *clk, int degrees) { - int ret = -EINVAL; + int ret; if (!clk) return 0; @@ -1908,17 +1927,7 @@ int clk_set_phase(struct clk *clk, int degrees) degrees += 360; clk_prepare_lock(); - - trace_clk_set_phase(clk->core, degrees); - - if (clk->core->ops->set_phase) - ret = clk->core->ops->set_phase(clk->core->hw, degrees); - - trace_clk_set_phase_complete(clk->core, degrees); - - if (!ret) - clk->core->phase = degrees; - + ret = clk_core_set_phase_nolock(clk->core, degrees); clk_prepare_unlock(); return ret; -- 2.13.5