From: Markus Trippelsdorf <markus@trippelsdorf.de>
To: Andy Lutomirski <luto@kernel.org>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
Borislav Petkov <bp@alien8.de>,
Adam Borowski <kilobyte@angband.pl>,
Brian Gerst <brgerst@gmail.com>
Subject: Re: [RFC PATCH] x86/mm: Flush more aggressively in lazy TLB mode
Date: Tue, 10 Oct 2017 10:22:57 +0200 [thread overview]
Message-ID: <20171010082257.GA12616@x4> (raw)
In-Reply-To: <8eccc9240041ea7cb94624cab8d07e2a6e911ba7.1507567665.git.luto@kernel.org>
On 2017.10.09 at 09:50 -0700, Andy Lutomirski wrote:
> Since commit 94b1b03b519b, x86's lazy TLB mode has been all the way
> lazy: when running a kernel thread (including the idle thread), the
> kernel keeps using the last user mm's page tables without attempting
> to maintain user TLB coherence at all. From a pure semantic
> perspective, this is fine -- kernel threads won't attempt to access
> user pages, so having stale TLB entries doesn't matter.
>
> Unfortunately, I forgot about a subtlety. By skipping TLB flushes,
> we also allow any paging-structure caches that may exist on the CPU
> to become incoherent. This means that we can have a
> paging-structure cache entry that references a freed page table, and
> the CPU is within its rights to do a speculative page walk starting
> at the freed page table.
>
> I can imagine this causing two different problems:
>
> - A speculative page walk starting from a bogus page table could read
> IO addresses. I haven't seen any reports of this causing problems.
>
> - A speculative page walk that involves a bogus page table can install
> garbage in the TLB. Such garbage would always be at a user VA, but
> some AMD CPUs have logic that triggers a machine check when it notices
> these bogus entries. I've seen a couple reports of this.
>
> Reinstate TLB coherence in lazy mode. With this patch applied, we
> do it in one of two ways. If we have PCID, we simply switch back to
> init_mm's page tables when we enter a kernel thread -- this seems to
> be quite cheap except for the cost of serializing the CPU. If we
> don't have PCID, then we set a flag and switch to init_mm the first
> time we would otherwise need to flush the TLB.
Your patch fixes the problem. (I've stressed my AMD machine in various
ways since yesterday. No issues thus far.)
Thanks.
--
Markus
prev parent reply other threads:[~2017-10-10 8:23 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-09 16:50 [RFC PATCH] x86/mm: Flush more aggressively in lazy TLB mode Andy Lutomirski
2017-10-09 17:02 ` Borislav Petkov
2017-10-09 17:36 ` Borislav Petkov
2017-10-09 17:50 ` Andy Lutomirski
2017-10-09 18:08 ` Borislav Petkov
2017-10-09 18:31 ` Andy Lutomirski
2017-10-13 9:07 ` demfloro
2017-10-14 10:49 ` [tip:x86/urgent] " tip-bot for Andy Lutomirski
2017-10-14 12:34 ` [PATCH] x86/mm: Rip out the TLB benchmarking knob Borislav Petkov
2017-10-14 17:01 ` Andy Lutomirski
2017-10-14 16:34 ` [tip:x86/urgent] x86/mm: Flush more aggressively in lazy TLB mode Andy Lutomirski
2017-10-14 17:00 ` Andy Lutomirski
2017-10-16 2:39 ` [lkp-robot] [x86/mm] c4c3c3c2d0: will-it-scale.per_process_ops -61.0% regression kernel test robot
2017-10-16 10:15 ` Borislav Petkov
2017-10-17 1:06 ` Andy Lutomirski
2017-10-17 4:57 ` Markus Trippelsdorf
2017-10-17 8:00 ` Borislav Petkov
2017-10-17 22:06 ` Andy Lutomirski
2017-10-18 14:26 ` Borislav Petkov
2017-10-18 1:59 ` Ye Xiaolong
2017-10-18 8:11 ` Borislav Petkov
2017-10-17 6:04 ` Ye Xiaolong
2017-10-10 8:22 ` Markus Trippelsdorf [this message]
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