From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752052AbdJXLnP (ORCPT ); Tue, 24 Oct 2017 07:43:15 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:45775 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751865AbdJXLnO (ORCPT ); Tue, 24 Oct 2017 07:43:14 -0400 X-Google-Smtp-Source: ABhQp+TZ1Y8gzXjebbRTREM3Eqcd5CIihUc9rtTro0+enaM+Dr2FcZY3ClwJ2JxIRZd4QnCVgxb6Pg== Date: Tue, 24 Oct 2017 14:43:11 +0300 From: "Kirill A. Shutemov" To: hpa@zytor.com Cc: Ingo Molnar , "Kirill A. Shutemov" , Linus Torvalds , x86@kernel.org, Thomas Gleixner , Andrew Morton , Andy Lutomirski , Cyrill Gorcunov , Borislav Petkov , linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/6] Boot-time switching between 4- and 5-level paging for 4.15, Part 1 Message-ID: <20171024114311.zmzhubtwpnegcvid@node.shutemov.name> References: <20170929140821.37654-1-kirill.shutemov@linux.intel.com> <20171003082754.no6ym45oirah53zp@node.shutemov.name> <20171017154241.f4zaxakfl7fcrdz5@node.shutemov.name> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 24, 2017 at 01:32:51PM +0200, hpa@zytor.com wrote: > On October 17, 2017 5:42:41 PM GMT+02:00, "Kirill A. Shutemov" wrote: > >On Tue, Oct 03, 2017 at 11:27:54AM +0300, Kirill A. Shutemov wrote: > >> On Fri, Sep 29, 2017 at 05:08:15PM +0300, Kirill A. Shutemov wrote: > >> > The first bunch of patches that prepare kernel to boot-time > >switching > >> > between paging modes. > >> > > >> > Please review and consider applying. > >> > >> Ping? > > > >Ingo, is there anything I can do to get review easier for you? > > > >I hoped to get boot-time switching code into v4.15... > > One issue that has come up with this is what happens if the kernel is > loaded above 4 GB and we need to switch page table mode. In that case > we need enough memory below the 4 GB point to hold a root page table > (since we can't write the upper half of cr3 outside of 64-bit mode) and > a handful of instructions. > > We have no real way to know for sure what memory is safe without parsing > all the memory maps and map out all the data structures that The > bootloader has left for the kernel. I'm thinking that the best way to > deal with this is to add an entry in setup_data to provide a pointers, > with the kernel header specifying a necessary size and alignment. I would appreciate your feedback on my take on this: http://lkml.kernel.org/r/20171020195934.32108-1-kirill.shutemov@linux.intel.com I don't change boot protocol, but trying to guess the safe spot in the way similar to what we do for realmode trampoline. -- Kirill A. Shutemov