From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, marc.zyngier@arm.com,
mark.rutland@arm.com, will.deacon@arm.com,
catalin.marinas@arm.com, robh@kernel.org, sudeep.holla@arm.com,
peterz@infradead.org, mathieu.poirier@linaro.org,
leo.yan@linaro.org, frowand.list@gmail.com,
Jonathan.Cameron@huawei.com, devicetree@vger.kernel.org,
Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v9 7/8] dt-bindings: Document devicetree binding for ARM DSU PMU
Date: Tue, 31 Oct 2017 17:23:17 +0000 [thread overview]
Message-ID: <20171031172318.11823-8-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20171031172318.11823-1-suzuki.poulose@arm.com>
This patch documents the devicetree bindings for ARM DSU PMU.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: devicetree@vger.kernel.org
Cc: frowand.list@gmail.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
Changes since V3:
- Fixed node name in the example, suggested by Rob
---
.../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ++++++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
new file mode 100644
index 000000000000..6efabba530f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
@@ -0,0 +1,27 @@
+* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
+
+ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
+with a shared L3 memory system, control logic and external interfaces to
+form a multicore cluster. The PMU enables to gather various statistics on
+the operations of the DSU. The PMU provides independent 32bit counters that
+can count any of the supported events, along with a 64bit cycle counter.
+The PMU is accessed via CPU system registers and has no MMIO component.
+
+** DSU PMU required properties:
+
+- compatible : should be one of :
+
+ "arm,dsu-pmu"
+
+- interrupts : Exactly 1 SPI must be listed.
+
+- cpus : List of phandles for the CPUs connected to this DSU instance.
+
+
+** Example:
+
+dsu-pmu-0 {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&cpu_0>, <&cpu_1>;
+};
--
2.13.6
next prev parent reply other threads:[~2017-10-31 17:26 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-31 17:23 [PATCH v9 0/8] perf: Support for ARM DynamIQ Shared Unit Suzuki K Poulose
2017-10-31 17:23 ` [PATCH v9 1/8] perf: Export perf_event_update_userpage Suzuki K Poulose
2017-11-03 11:16 ` Mark Rutland
2017-10-31 17:23 ` [PATCH v9 2/8] of: Add helper for mapping device node to logical CPU number Suzuki K Poulose
2017-10-31 17:23 ` [PATCH v9 3/8] coresight: of: Use of_cpu_node_to_id helper Suzuki K Poulose
2017-10-31 17:23 ` [PATCH v9 4/8] irqchip: gic-v3: " Suzuki K Poulose
2017-10-31 17:23 ` [PATCH v9 5/8] arm64: Use of_cpu_node_to_id helper for CPU topology parsing Suzuki K Poulose
2017-10-31 17:23 ` [PATCH v9 6/8] arm_pmu: Use of_cpu_node_to_id helper Suzuki K Poulose
2017-10-31 17:23 ` Suzuki K Poulose [this message]
2017-10-31 17:23 ` [PATCH v9 8/8] perf: ARM DynamIQ Shared Unit PMU support Suzuki K Poulose
2017-11-03 12:20 ` Mark Rutland
2017-11-03 14:34 ` Suzuki K Poulose
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