From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752399AbdKKXP0 (ORCPT ); Sat, 11 Nov 2017 18:15:26 -0500 Received: from mail-pf0-f193.google.com ([209.85.192.193]:50398 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751607AbdKKXPY (ORCPT ); Sat, 11 Nov 2017 18:15:24 -0500 X-Google-Smtp-Source: AGs4zMbONmmZOSZHOagwbK8VswV+tYGhLIj3yjP8exd7A3G4qjVjte7XJb64nW6Uk7Ojv99+s7FDYg== Date: Sat, 11 Nov 2017 15:15:21 -0800 From: Guenter Roeck To: Andi Kleen Cc: x86@kernel.org, hpa@zytor.com, linux-kernel@vger.kernel.org, Andi Kleen Subject: Re: [v8, 4/5] x86/xsave: Make XSAVE check the base CPUID features before enabling Message-ID: <20171111231521.GA31139@roeck-us.net> References: <20171005215256.25659-5-andi@firstfloor.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20171005215256.25659-5-andi@firstfloor.org> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 05, 2017 at 02:52:55PM -0700, Andi Kleen wrote: > From: Andi Kleen > > Before enabling XSAVE, not only check the XSAVE specific CPUID bits, > but also the base CPUID features of the respective XSAVE feature. > This allows to disable individual XSAVE states using the existing > clearcpuid= option, which can be useful for performance testing > and debugging, and also in general avoids inconsistencies. > > v2: > Add curly brackets (Thomas Gleixner) > Signed-off-by: Andi Kleen this patch makes qemu spit out the following warning, possibly because it doesn't support all expected CPUID features for the various CPUs. WARNING: CPU: 0 PID: 0 at arch/x86/kernel/fpu/xstate.c:614 fpu__init_system_xstate+0x403/0x721 with associated traceback. I understand that this is a qemu problem, but does the traceback really add value ? Guenter > --- > arch/x86/kernel/fpu/xstate.c | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c > index f1d5476c9022..924bd895b5ee 100644 > --- a/arch/x86/kernel/fpu/xstate.c > +++ b/arch/x86/kernel/fpu/xstate.c > @@ -15,6 +15,7 @@ > #include > > #include > +#include > > /* > * Although we spell it out in here, the Processor Trace > @@ -36,6 +37,19 @@ static const char *xfeature_names[] = > "unknown xstate feature" , > }; > > +static short xsave_cpuid_features[] = { > + X86_FEATURE_FPU, > + X86_FEATURE_XMM, > + X86_FEATURE_AVX, > + X86_FEATURE_MPX, > + X86_FEATURE_MPX, > + X86_FEATURE_AVX512F, > + X86_FEATURE_AVX512F, > + X86_FEATURE_AVX512F, > + X86_FEATURE_INTEL_PT, > + X86_FEATURE_PKU, > +}; > + > /* > * Mask of xstate features supported by the CPU and the kernel: > */ > @@ -726,6 +740,7 @@ void __init fpu__init_system_xstate(void) > unsigned int eax, ebx, ecx, edx; > static int on_boot_cpu __initdata = 1; > int err; > + int i; > > WARN_ON_FPU(!on_boot_cpu); > on_boot_cpu = 0; > @@ -759,6 +774,14 @@ void __init fpu__init_system_xstate(void) > goto out_disable; > } > > + /* > + * Clear XSAVE features that are disabled in the normal CPUID. > + */ > + for (i = 0; i < ARRAY_SIZE(xsave_cpuid_features); i++) { > + if (!boot_cpu_has(xsave_cpuid_features[i])) > + xfeatures_mask &= ~BIT(i); > + } > + > xfeatures_mask &= fpu__get_supported_xfeatures_mask(); > > /* Enable xstate instructions to be able to continue with initialization: */