From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751874AbdKZTd4 (ORCPT ); Sun, 26 Nov 2017 14:33:56 -0500 Received: from mail-pl0-f68.google.com ([209.85.160.68]:44204 "EHLO mail-pl0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751510AbdKZTdy (ORCPT ); Sun, 26 Nov 2017 14:33:54 -0500 X-Google-Smtp-Source: AGs4zMaIw1VuX8mP65c+TN39sKvjQxrFDzj8sFTLygR9/WDo7Yq1TAHYkArZ39zwGb3FiPjzF7Abqg== Date: Sun, 26 Nov 2017 13:33:50 -0600 From: Rob Herring To: Cyrille Pitchen Cc: bhelgaas@google.com, kishon@ti.com, lorenzo.pieralisi@arm.com, linux-pci@vger.kernel.org, adouglas@cadence.com, stelford@cadence.com, dgary@cadence.com, kgopi@cadence.com, eandrews@cadence.com, thomas.petazzoni@free-electrons.com, sureshp@cadence.com, nsekhar@ti.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 4/5] dt-bindings: PCI: cadence: Add DT bindings for Cadence PCIe endpoint controller Message-ID: <20171126193350.4ortdptrxdibnyot@rob-hp-laptop> References: <0a11e9742db04fd5b4bc08568b3ab5a056a0ef9d.1511439189.git.cyrille.pitchen@free-electrons.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <0a11e9742db04fd5b4bc08568b3ab5a056a0ef9d.1511439189.git.cyrille.pitchen@free-electrons.com> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 23, 2017 at 04:01:49PM +0100, Cyrille Pitchen wrote: > This patch documents the DT bindings for the Cadence PCIe controller > when configured in endpoint mode. > > Signed-off-by: Cyrille Pitchen > --- > .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt Acked-by: Rob Herring