From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752815AbdK1DYr (ORCPT ); Mon, 27 Nov 2017 22:24:47 -0500 Received: from mga11.intel.com ([192.55.52.93]:22671 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751623AbdK1DYp (ORCPT ); Mon, 27 Nov 2017 22:24:45 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,466,1505804400"; d="scan'208";a="1249295126" Date: Tue, 28 Nov 2017 11:15:19 +0800 From: Wu Hao To: David Laight Cc: "atull@kernel.org" , "mdf@kernel.org" , "linux-fpga@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-api@vger.kernel.org" , "luwei.kang@intel.com" , "yi.z.zhang@intel.com" , Tim Whisonant , Enno Luebbers , Shiva Rao , Christopher Rauer , Xiao Guangrong Subject: Re: [PATCH v3 08/21] fpga: add Intel FPGA DFL PCIe device Message-ID: <20171128031519.GA25705@hao-dev> References: <1511764948-20972-1-git-send-email-hao.wu@intel.com> <1511764948-20972-9-git-send-email-hao.wu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 27, 2017 at 10:28:04AM +0000, David Laight wrote: > From: Wu Hao > > Sent: 27 November 2017 06:42 > > From: Zhang Yi > > > > The Intel FPGA device appears as a PCIe device on the system. This patch > > implements the basic framework of the driver for Intel PCIe device which > > is located between CPU and Accelerated Function Units (AFUs), and has > > the Device Feature List (DFL) implemented in its MMIO space. > > This ought to have a better name than 'Intel FPGA'. > An fpga can be used for all sorts of things, this looks like > a very specific architecture using a common VHDL environment to > allow certain types of user VHDL be accessed over PCIe. Hi David This patch adds a pcie device driver for Intel FPGA devices which implements the DFL, e.g Intel Server Platform with In-package FPGA and Intel FPGA PCIe Acceleration Cards. They are pcie devices, and all have DFL implemented in the MMIO space, so we would like to use one kernel driver to handle them. With this full patchset, it just provides user the interfaces to configure and access the FPGA accelerators on Intel DFL based FPGA devices. For sure, users can develop and build their own logics via tools provided by Intel, program them to accelerators on these Intel FPGA devices, and access them for their workloads. Thanks Hao