From: Alexandre Belloni <alexandre.belloni@free-electrons.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org,
Alexandre Belloni <alexandre.belloni@free-electrons.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, Jason Cooper <jason@lakedaemon.net>
Subject: [PATCH 02/13] dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller
Date: Tue, 28 Nov 2017 16:26:32 +0100 [thread overview]
Message-ID: <20171128152643.20463-3-alexandre.belloni@free-electrons.com> (raw)
In-Reply-To: <20171128152643.20463-1-alexandre.belloni@free-electrons.com>
Add the Device Tree binding documentation for the Microsemi Ocelot
interrupt controller that is part of the ICPU. It is connected directly to
the MIPS core interrupt controller.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
.../interrupt-controller/mscc,ocelot-icpu-intr.txt | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
new file mode 100644
index 000000000000..b47a8a02b17b
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
@@ -0,0 +1,22 @@
+Microsemi Ocelot SoC ICPU Interrupt Controller
+
+Required properties:
+
+- compatible : should be "mscc,ocelot-icpu-intr"
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+- interrupt-parent : phandle of the CPU interrupt controller.
+- interrupts : Specifies the CPU interrupt the controller is connected to.
+
+Example:
+
+ intc: interrupt-controller@70000070 {
+ compatible = "mscc,ocelot-icpu-intr";
+ reg = <0x70000070 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
--
2.15.0
next prev parent reply other threads:[~2017-11-28 15:27 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-28 15:26 [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni
2017-11-28 15:26 ` [PATCH 01/13] dt-bindings: Add vendor prefix for Microsemi Corporation Alexandre Belloni
2017-11-28 16:10 ` James Hogan
2017-11-28 16:22 ` Alexandre Belloni
2017-12-01 1:14 ` Rob Herring
2017-11-28 15:26 ` Alexandre Belloni [this message]
2017-12-01 1:15 ` [PATCH 02/13] dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller Rob Herring
2017-11-28 15:26 ` [PATCH 03/13] irqchip: Add a driver for the Microsemi Ocelot controller Alexandre Belloni
2017-11-28 15:26 ` [PATCH 04/13] dt-bindings: pinctrl: Add bindings for Microsemi Ocelot Alexandre Belloni
2017-12-01 1:16 ` Rob Herring
2017-11-28 15:26 ` [PATCH 05/13] pinctrl: Add Microsemi Ocelot SoC driver Alexandre Belloni
2017-11-28 15:26 ` [PATCH 06/13] dt-bindings: power: reset: Document ocelot-reset binding Alexandre Belloni
2017-12-01 1:54 ` Rob Herring
2017-11-28 15:26 ` [PATCH 07/13] power: reset: Add a driver for the Microsemi Ocelot reset Alexandre Belloni
2017-11-28 15:26 ` [PATCH 08/13] dt-bindings: mips: Add bindings for Microsemi SoCs Alexandre Belloni
2017-11-28 19:14 ` Florian Fainelli
2017-11-28 15:26 ` [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS SoCs Alexandre Belloni
2017-11-28 16:01 ` James Hogan
2017-11-28 16:53 ` Alexandre Belloni
2017-11-28 17:31 ` James Hogan
2017-11-28 19:50 ` Paul Burton
2017-11-29 16:38 ` Alexandre Belloni
2018-01-17 23:58 ` James Hogan
2018-03-02 15:22 ` Alexandre Belloni
2017-11-28 15:26 ` [PATCH 10/13] MIPS: mscc: add ocelot dtsi Alexandre Belloni
2017-11-28 18:40 ` Florian Fainelli
2017-11-28 15:26 ` [PATCH 11/13] MIPS: mscc: add ocelot PCB123 device tree Alexandre Belloni
2017-11-28 15:26 ` [PATCH 12/13] MIPS: defconfigs: add a defconfig for Microsemi SoCs Alexandre Belloni
2017-11-28 15:26 ` [PATCH 13/13] MAINTAINERS: Add entry for Microsemi MIPS SoCs Alexandre Belloni
2017-11-28 15:34 ` Joe Perches
2017-11-28 15:44 ` Alexandre Belloni
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20171128152643.20463-3-alexandre.belloni@free-electrons.com \
--to=alexandre.belloni@free-electrons.com \
--cc=devicetree@vger.kernel.org \
--cc=jason@lakedaemon.net \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@linux-mips.org \
--cc=ralf@linux-mips.org \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).