From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753945AbdK1P2A (ORCPT ); Tue, 28 Nov 2017 10:28:00 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:36949 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753846AbdK1P1z (ORCPT ); Tue, 28 Nov 2017 10:27:55 -0500 From: Alexandre Belloni To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Alexandre Belloni , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH 08/13] dt-bindings: mips: Add bindings for Microsemi SoCs Date: Tue, 28 Nov 2017 16:26:38 +0100 Message-Id: <20171128152643.20463-9-alexandre.belloni@free-electrons.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171128152643.20463-1-alexandre.belloni@free-electrons.com> References: <20171128152643.20463-1-alexandre.belloni@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add bindings for Microsemi SoCs. Currently only Ocelot is supported. Signed-off-by: Alexandre Belloni --- Cc: Rob Herring Cc: devicetree@vger.kernel.org Documentation/devicetree/bindings/mips/mscc.txt | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt new file mode 100644 index 000000000000..2c52e76b7142 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/mscc.txt @@ -0,0 +1,6 @@ +* Microsemi MIPS CPUs + +Required properties: +- compatible: "brcm,ocelot" + +- mips-hpt-frequency: CPU counter frequency. -- 2.15.0