From: Alexandre Belloni <alexandre.belloni@free-electrons.com>
To: Paul Burton <paul.burton@mips.com>
Cc: James Hogan <james.hogan@mips.com>,
Ralf Baechle <ralf@linux-mips.org>,
linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS SoCs
Date: Wed, 29 Nov 2017 17:38:19 +0100 [thread overview]
Message-ID: <20171129163819.GN21126@piout.net> (raw)
In-Reply-To: <20171128195002.dcq7i2wqmstkn3rr@pburton-laptop>
Hi Paul,
On 28/11/2017 at 11:50:02 -0800, Paul Burton wrote:
> On Tue, Nov 28, 2017 at 05:31:51PM +0000, James Hogan wrote:
> > On Tue, Nov 28, 2017 at 05:53:59PM +0100, Alexandre Belloni wrote:
> > > On 28/11/2017 at 16:01:38 +0000, James Hogan wrote:
> > > > On Tue, Nov 28, 2017 at 04:26:39PM +0100, Alexandre Belloni wrote:
> > > > > Introduce support for the MIPS based Microsemi Ocelot SoCs.
> > > > > As the plan is to have all SoCs supported only using device tree, the
> > > > > mach directory is simply called mscc.
> > > >
> > > > Nice. Have you considered adding this to the existing multiplatform
> > > > "generic" platform? See for example commit b35565bb16a5 ("MIPS: generic:
> > > > Add support for MIPSfpga") for the latest platform to be converted.
> > > >
> > >
> > > I didn't because we are currently booting using an old redboot with its
> > > own boot protocol and at boot, the register read by the sead3 code is
> > > completely random (it actually matched once).
> > >
> > > Do you consider that mandatory to get the platform upstream?
> >
> > No, however if it is practical to do so I think it might be the best way
> > forward (even if generic+YAMON support is mutually exclusive of
> > generic+redboot, though hopefully there is some way to avoid that).
> >
> > Paul on Cc, he may have thoughts on this one.
>
> We could certainly look at tightening the checks in the SEAD-3 code to
> avoid the false positive.
>
> Could you share any details of the boot protocol you're using with
> redboot? One option might be for the SEAD-3 code to check that the
> arguments the bootloader provided look "YAMON-like", so long as the 2
> protocols differ sufficiently.
>
I didn't look closely at the redboot code yet but it ends up with
something like:
- argc == fw_arg0
- argv == fw_arg1
- not sure yet what is in argv[0]
- kernel commande line in argv[1]
- fw_arg2 is a pointer to a structure like:
struct parmblock {
t_env_var memsize;
};
with:
typedef struct
{
char *name;
char *val;
} t_env_var;
this is the size of the RAM but I'm not using it because it is in the
device tree.
Does that help?
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
next prev parent reply other threads:[~2017-11-29 16:38 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-28 15:26 [PATCH 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni
2017-11-28 15:26 ` [PATCH 01/13] dt-bindings: Add vendor prefix for Microsemi Corporation Alexandre Belloni
2017-11-28 16:10 ` James Hogan
2017-11-28 16:22 ` Alexandre Belloni
2017-12-01 1:14 ` Rob Herring
2017-11-28 15:26 ` [PATCH 02/13] dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller Alexandre Belloni
2017-12-01 1:15 ` Rob Herring
2017-11-28 15:26 ` [PATCH 03/13] irqchip: Add a driver for the Microsemi Ocelot controller Alexandre Belloni
2017-11-28 15:26 ` [PATCH 04/13] dt-bindings: pinctrl: Add bindings for Microsemi Ocelot Alexandre Belloni
2017-12-01 1:16 ` Rob Herring
2017-11-28 15:26 ` [PATCH 05/13] pinctrl: Add Microsemi Ocelot SoC driver Alexandre Belloni
2017-11-28 15:26 ` [PATCH 06/13] dt-bindings: power: reset: Document ocelot-reset binding Alexandre Belloni
2017-12-01 1:54 ` Rob Herring
2017-11-28 15:26 ` [PATCH 07/13] power: reset: Add a driver for the Microsemi Ocelot reset Alexandre Belloni
2017-11-28 15:26 ` [PATCH 08/13] dt-bindings: mips: Add bindings for Microsemi SoCs Alexandre Belloni
2017-11-28 19:14 ` Florian Fainelli
2017-11-28 15:26 ` [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS SoCs Alexandre Belloni
2017-11-28 16:01 ` James Hogan
2017-11-28 16:53 ` Alexandre Belloni
2017-11-28 17:31 ` James Hogan
2017-11-28 19:50 ` Paul Burton
2017-11-29 16:38 ` Alexandre Belloni [this message]
2018-01-17 23:58 ` James Hogan
2018-03-02 15:22 ` Alexandre Belloni
2017-11-28 15:26 ` [PATCH 10/13] MIPS: mscc: add ocelot dtsi Alexandre Belloni
2017-11-28 18:40 ` Florian Fainelli
2017-11-28 15:26 ` [PATCH 11/13] MIPS: mscc: add ocelot PCB123 device tree Alexandre Belloni
2017-11-28 15:26 ` [PATCH 12/13] MIPS: defconfigs: add a defconfig for Microsemi SoCs Alexandre Belloni
2017-11-28 15:26 ` [PATCH 13/13] MAINTAINERS: Add entry for Microsemi MIPS SoCs Alexandre Belloni
2017-11-28 15:34 ` Joe Perches
2017-11-28 15:44 ` Alexandre Belloni
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20171129163819.GN21126@piout.net \
--to=alexandre.belloni@free-electrons.com \
--cc=james.hogan@mips.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@linux-mips.org \
--cc=paul.burton@mips.com \
--cc=ralf@linux-mips.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).