From: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
To: intel-sgx-kernel-dev@lists.01.org,
platform-driver-x86@vger.kernel.org, x86@kernel.org
Cc: linux-kernel@vger.kernel.org,
Kai Huang <kai.huang@linux.intel.com>,
Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
Borislav Petkov <bp@suse.de>,
Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Kyle Huey <me@kylehuey.com>
Subject: [PATCH v9 2/7] x86: add SGX definitions to cpufeature
Date: Sat, 16 Dec 2017 18:19:49 +0200 [thread overview]
Message-ID: <20171216162200.20243-3-jarkko.sakkinen@linux.intel.com> (raw)
In-Reply-To: <20171216162200.20243-1-jarkko.sakkinen@linux.intel.com>
From: Kai Huang <kai.huang@linux.intel.com>
Added X86_FEATURE_SGX and X86_FEATURE_SGX_LC definitions that define the
bits CPUID level 7 bits for determining whether the CPU supports SGX and
launch configuration other than the Intel proprietary key. If this the
case, IA32_SGXLEPUBKEYHASHn MSRs (0 < n < 4) are available for defining
the root key for enclaves.
Signed-off-by: Kai Huang <kai.huang@linux.intel.com>
Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
Tested-by: Serge Ayoun <serge.ayoun@intel.com>
---
arch/x86/include/asm/cpufeatures.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index c0b0e9e8aa66..a3fca410216e 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -223,6 +223,7 @@
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3B */
+#define X86_FEATURE_SGX ( 9*32+ 2) /* Software Guard Extensions */
#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */
#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */
#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */
@@ -308,6 +309,7 @@
#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
#define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */
#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */
+#define X86_FEATURE_SGX_LC (16*32+30) /* supports SGX launch configuration */
/* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
#define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */
--
2.14.1
next prev parent reply other threads:[~2017-12-16 16:26 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-16 16:19 [PATCH v9 0/7] Intel SGX Driver Jarkko Sakkinen
2017-12-16 16:19 ` [PATCH v9 1/7] intel_sgx: updated MAINTAINERS Jarkko Sakkinen
2017-12-16 16:19 ` Jarkko Sakkinen [this message]
2017-12-16 16:19 ` [PATCH v9 3/7] x86: add SGX definitions to msr-index.h Jarkko Sakkinen
2017-12-16 16:19 ` [PATCH v9 4/7] intel_sgx: driver for Intel Software Guard Extensions Jarkko Sakkinen
2017-12-16 18:31 ` Philippe Ombredanne
2017-12-17 16:01 ` Jarkko Sakkinen
2017-12-16 16:19 ` [PATCH v9 5/7] intel_sgx: ptrace() support Jarkko Sakkinen
2017-12-16 16:19 ` [PATCH v9 6/7] intel_sgx: driver documentation Jarkko Sakkinen
2017-12-16 16:19 ` [PATCH v9 7/7] intel_sgx: in-kernel launch enclave Jarkko Sakkinen
2017-12-19 13:59 ` Jarkko Sakkinen
2017-12-19 15:36 ` Andy Shevchenko
2017-12-19 23:57 ` Jarkko Sakkinen
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