From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758318AbdLRJcX (ORCPT ); Mon, 18 Dec 2017 04:32:23 -0500 Received: from mx0a-001ae601.pphosted.com ([67.231.149.25]:41458 "EHLO mx0b-001ae601.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1758304AbdLRJcT (ORCPT ); Mon, 18 Dec 2017 04:32:19 -0500 Authentication-Results: ppops.net; spf=none smtp.mailfrom=ckeepax@opensource.cirrus.com Date: Mon, 18 Dec 2017 09:31:22 +0000 From: Charles Keepax To: chen liu CC: , , , , , , , , Subject: Re: [PATCH v2] ASOC: wm8960: Add multiple MCLK frequency support Message-ID: <20171218093122.mgghz4mkxtvix6uu@localhost.localdomain> References: <1513168650-102028-1-git-send-email-chen.liu.opensource@gmail.com> <20171214161954.wfik3ygadwii3zhm@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1711220000 definitions=main-1712180125 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Dec 15, 2017 at 09:07:15PM +0800, chen liu wrote: > 2017-12-15 0:19 GMT+08:00 Charles Keepax : > > On Wed, Dec 13, 2017 at 08:37:30PM +0800, Chen.Liu wrote: > When the MCLK clock frequency cannot meet the SYSCLK clock > frequency of the wm8960 codec,we must use the PLL divider to > generate the clock frequency. > > For what you are talking about setting the SYSCLK clock frequency > automatically and manually,the difference is that one uses the PLL > divider to generate the SYSCLK clock frequency and the other one > provides the SYSCLK clock frequency directly through the MCLK. > > Although the driver already supports setting the SYSCLK_DIV register, > it can only be set to 1,thus causing the codec to not support multiple > MCLK clock frequency.(For more information, please see the wm8960 > codec manual) > > The important purpose of this patch is to support multiple MCLK > clock frequency. Sorry I think I am not following something here, could you be a bit more specific, especially about why the automatic approach doesn't meet your needs. As far as I can see this will let you set the SYSCLKDIV using the manual method and it can be easily set to either 1 or 2: static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai, ... switch (div_id) { case WM8960_SYSCLKDIV: reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1f9; snd_soc_write(codec, WM8960_CLOCK1, reg | div); break; ... And as for the automatic method: static int wm8960_configure_pll(struct snd_soc_codec *codec, int freq_in, ... for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) { if (sysclk_divs[i] == -1) continue; ... This will iterate through all the sysclk_dividers and pick one that is appropriate either 1 or 2. So in what way does the automatic method not support a SYSCLK_DIV of 2? Thanks, Charles