From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933310AbdLRMFx (ORCPT ); Mon, 18 Dec 2017 07:05:53 -0500 Received: from mx0a-001ae601.pphosted.com ([67.231.149.25]:51680 "EHLO mx0b-001ae601.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1758084AbdLRMFk (ORCPT ); Mon, 18 Dec 2017 07:05:40 -0500 Authentication-Results: ppops.net; spf=none smtp.mailfrom=ckeepax@opensource.cirrus.com Date: Mon, 18 Dec 2017 11:55:26 +0000 From: Charles Keepax To: chen liu CC: Liam Girdwood , , , , , , , , Subject: Re: [PATCH v2] ASOC: wm8960: Add multiple MCLK frequency support Message-ID: <20171218115526.z336fwohv5mt45sk@localhost.localdomain> References: <1513168650-102028-1-git-send-email-chen.liu.opensource@gmail.com> <20171214161954.wfik3ygadwii3zhm@localhost.localdomain> <20171218093122.mgghz4mkxtvix6uu@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1711220000 definitions=main-1712180162 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Dec 18, 2017 at 07:32:41PM +0800, chen liu wrote: > 2017-12-18 17:31 GMT+08:00 Charles Keepax : > > > On Fri, Dec 15, 2017 at 09:07:15PM +0800, chen liu wrote: > > > 2017-12-15 0:19 GMT+08:00 Charles Keepax > >: > > > > On Wed, Dec 13, 2017 at 08:37:30PM +0800, Chen.Liu wrote: > According to your detailed description above, I understand what you mean. > For the 'wm8960_configure_pll' function,it deduces a reasonable PLL output > clock frequency based on the 'freq_in' frequency,the sample rate,and the bit > clock. > > static int wm8960_configure_clocking(struct snd_soc_codec*codec) > ... > freq_out = wm8960_configure_pll(codec, freq_in, &i, &j, &k); > if (freq_out < 0) { > dev_err(codec->dev, "failed to configure clock via PLL\n"); > return freq_out; > } > wm8960_set_pll(codec, freq_in, freq_out); > ... > > In the 'wm8960_configure_clocking' function, it sets the PLL divider by > calling > the 'wm8960_set_pll' function after calling the 'wm8960_configure_pll'. > However,there is no support for SYSCLK_DIV = 2 in the 'wm8960_set_pll' > function. > > Looking forward to your reply. Indeed yes, as it looks like the intention was you would set the SYSCLKDIV manually if setting the PLL manually. But why not just call wm8960_set_pll will WM8960_SYSCLK_AUTO, and then your code will use the configure_pll stuff? I would like to understand what about that approach isn't working for you as that seems like the easiest solution. Thanks, Charles