From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030243AbdLSJp6 (ORCPT ); Tue, 19 Dec 2017 04:45:58 -0500 Received: from fllnx210.ext.ti.com ([198.47.19.17]:35485 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934217AbdLSJpz (ORCPT ); Tue, 19 Dec 2017 04:45:55 -0500 From: Kishon Vijay Abraham I To: Rob Herring , Mark Rutland , CC: , , , Subject: [PATCH 0/2] ti-pipe3: PCIe x2 lane mode configuration in dra72 Date: Tue, 19 Dec 2017 15:15:38 +0530 Message-ID: <20171219094540.18432-1-kishon@ti.com> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org DRA72 uses the same pipe3 PHY for the 2nd lane of PCIE and USB3 PHY. By default it is configured to be used as USB3 PHY and some special configuration has to be done inorder to use it for the 2nd lane of PCIE. This series adds a new dt property and the configuration required to enable 2nd lane of PCIE. Kishon Vijay Abraham I (2): dt-bindings: phy: ti-pipe3: Add dt binding to use USB3 PHY for PCIe phy: ti-pipe3: configure usb3 phy to be used as pcie phy Documentation/devicetree/bindings/phy/ti-phy.txt | 2 + drivers/phy/ti/phy-ti-pipe3.c | 47 +++++++++++++++++++++--- 2 files changed, 43 insertions(+), 6 deletions(-) -- 2.11.0