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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>, <kishon@ti.com>
Cc: <devicetree@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <nsekhar@ti.com>
Subject: [PATCH 1/2] dt-bindings: phy: ti-pipe3: Add dt binding to use USB3 PHY for PCIe
Date: Tue, 19 Dec 2017 15:15:39 +0530	[thread overview]
Message-ID: <20171219094540.18432-2-kishon@ti.com> (raw)
In-Reply-To: <20171219094540.18432-1-kishon@ti.com>

DRA72 uses USB3 PHY for the 2nd lane of PCIE. Add dt bindings property
to indicate if the USB3 PHY should be used for 2nd lane of PCIe.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 Documentation/devicetree/bindings/phy/ti-phy.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt
index cd13e6157088..907a046e794b 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -93,6 +93,8 @@ Optional properties:
    register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
  - syscon-pcs : phandle/offset pair. Phandle to the system control module and the
    register offset to write the PCS delay value.
+ - "ti,configure-as-pcie" : property to indicate if the PHY should be
+   configured as PCIE PHY.
 
 Deprecated properties:
  - ctrl-module : phandle of the control module used by PHY driver to power on
-- 
2.11.0

  reply	other threads:[~2017-12-19  9:46 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-19  9:45 [PATCH 0/2] ti-pipe3: PCIe x2 lane mode configuration in dra72 Kishon Vijay Abraham I
2017-12-19  9:45 ` Kishon Vijay Abraham I [this message]
2017-12-20 20:55   ` [PATCH 1/2] dt-bindings: phy: ti-pipe3: Add dt binding to use USB3 PHY for PCIe Rob Herring
2017-12-19  9:45 ` [PATCH 2/2] phy: ti-pipe3: configure usb3 phy to be used as pcie phy Kishon Vijay Abraham I

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