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From: Peter Zijlstra <peterz@infradead.org>
To: tglx@linutronix.de, linux-kernel@vger.kernel.org
Cc: x86@kernel.org, peterz@infradead.org, rui.zhang@intel.com,
	len.brown@intel.com
Subject: [PATCH 1/3] x86/tsc: Allow TSC calibration without PIT
Date: Fri, 22 Dec 2017 10:20:11 +0100
Message-ID: <20171222092243.333145937@infradead.org> (raw)
In-Reply-To: <20171222092010.732743589@infradead.org>


[-- Attachment #0: peterz-no-pit.patch --]
[-- Type: text/plain, Size: 2250 bytes --]

Zhang Rui reported that a Surface Pro 4 will fail to boot with
lapic=notscdeadline. Part of the problem is that that machine doesn't
have a PIC.

If, for some reason, we fall back to TSC calibration, we rely on the
PIT to be present. Allow TSC calibration to reliably fall back to
HPET.

The below results in an accurate TSC measurement when forced on my
IVB:

  tsc: Unable to calibrate against PIT
  tsc: No reference (HPET/PMTIMER) available
  tsc: Unable to calibrate against PIT
  tsc: using HPET reference calibration
  tsc: Detected 2792.451 MHz processor

Cc: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
 arch/x86/include/asm/i8259.h |    5 +++++
 arch/x86/kernel/tsc.c        |   18 ++++++++++++++++++
 2 files changed, 23 insertions(+)

--- a/arch/x86/include/asm/i8259.h
+++ b/arch/x86/include/asm/i8259.h
@@ -69,6 +69,11 @@ struct legacy_pic {
 extern struct legacy_pic *legacy_pic;
 extern struct legacy_pic null_legacy_pic;
 
+static inline bool has_legacy_pic(void)
+{
+	return legacy_pic != &null_legacy_pic;
+}
+
 static inline int nr_legacy_irqs(void)
 {
 	return legacy_pic->nr_legacy_irqs;
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -25,6 +25,7 @@
 #include <asm/geode.h>
 #include <asm/apic.h>
 #include <asm/intel-family.h>
+#include <asm/i8259.h>
 
 unsigned int __read_mostly cpu_khz;	/* TSC clocks / usec, not used here */
 EXPORT_SYMBOL(cpu_khz);
@@ -363,6 +364,20 @@ static unsigned long pit_calibrate_tsc(u
 	unsigned long tscmin, tscmax;
 	int pitcnt;
 
+	if (!has_legacy_pic()) {
+		/*
+		 * Relies on tsc_early_delay_calibrate() to have given us semi
+		 * usable udelay(), wait for the same 50ms we would have with
+		 * the PIT loop below.
+		 */
+		udelay(10 * USEC_PER_MSEC);
+		udelay(10 * USEC_PER_MSEC);
+		udelay(10 * USEC_PER_MSEC);
+		udelay(10 * USEC_PER_MSEC);
+		udelay(10 * USEC_PER_MSEC);
+		return ULONG_MAX;
+	}
+
 	/* Set the Gate high, disable speaker */
 	outb((inb(0x61) & ~0x02) | 0x01, 0x61);
 
@@ -487,6 +502,9 @@ static unsigned long quick_pit_calibrate
 	u64 tsc, delta;
 	unsigned long d1, d2;
 
+	if (!has_legacy_pic())
+		return 0;
+
 	/* Set the Gate high, disable speaker */
 	outb((inb(0x61) & ~0x02) | 0x01, 0x61);
 

  reply index

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-22  9:20 [PATCH 0/3] x86 time bits Peter Zijlstra
2017-12-22  9:20 ` Peter Zijlstra [this message]
2018-01-14 19:21   ` [tip:x86/timers] x86/tsc: Allow TSC calibration without PIT tip-bot for Peter Zijlstra
2017-12-22  9:20 ` [PATCH 2/3] x86/time: Unconditionally register legacy timer interrupt Peter Zijlstra
2018-01-14 19:22   ` [tip:x86/timers] " tip-bot for Peter Zijlstra
2017-12-22  9:20 ` [PATCH 3/3] x86/tsc: Introduce early tsc clocksource Peter Zijlstra
2018-01-14 19:22   ` [tip:x86/timers] " tip-bot for Peter Zijlstra

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