From: Will Deacon <will.deacon@arm.com>
To: James Morse <james.morse@arm.com>
Cc: marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org,
catalin.marinas@arm.com, ard.biesheuvel@linaro.org,
lorenzo.pieralisi@arm.com, christoffer.dall@linaro.org,
linux-kernel@vger.kernel.org, labbott@redhat.com
Subject: Re: [PATCH v2 07/11] arm64: Add skeleton to harden the branch predictor against aliasing attacks
Date: Mon, 8 Jan 2018 14:26:57 +0000 [thread overview]
Message-ID: <20180108142657.GE25869@arm.com> (raw)
In-Reply-To: <5A53611C.5030003@arm.com>
Hi James,
Thanks for having a look.
On Mon, Jan 08, 2018 at 12:16:28PM +0000, James Morse wrote:
> On 05/01/18 13:12, Will Deacon wrote:
> > diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
> > index 22168cd0dde7..5203b6040cb6 100644
> > --- a/arch/arm64/mm/fault.c
> > +++ b/arch/arm64/mm/fault.c
> > @@ -318,6 +318,7 @@ static void __do_user_fault(struct task_struct *tsk, unsigned long addr,
> > lsb = PAGE_SHIFT;
> > si.si_addr_lsb = lsb;
> >
> > + arm64_apply_bp_hardening();
>
> Due to the this_cpu_ptr() call:
>
> | BUG: using smp_processor_id() in preemptible [00000000] code: print_my_pa/2093
> | caller is debug_smp_processor_id+0x1c/0x24
> | CPU: 0 PID: 2093 Comm: print_my_pa Tainted: G W
> 4.15.0-rc3-00044-g7f0aaec94f27-dirty #8950
> | Call trace:
> | dump_backtrace+0x0/0x164
> | show_stack+0x14/0x1c
> | dump_stack+0xa4/0xdc
> | check_preemption_disabled+0xfc/0x100
> | debug_smp_processor_id+0x1c/0x24
> | __do_user_fault+0xcc/0x180
> | do_page_fault+0x14c/0x364
> | do_translation_fault+0x40/0x48
> | do_mem_abort+0x40/0xb8
> | el0_da+0x20/0x24
Ah bugger, yes, we re-enabled interrupts in the entry code when we took the
fault initially.
> Make it a TIF flag?
>
> (Seen with arm64's kpti-base tag and this series)
A TIF flag is still a bit fiddly, because we need to track that the
predictor could be dirty on this CPU. Instead, I'll postpone the re-enabling
of IRQs on el0_ia until we're in C code -- we can quickly a check on the
address before doing that. See below.
Will
--->8
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 80b539845da6..07a7d4db8ec4 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -721,12 +721,15 @@ el0_ia:
* Instruction abort handling
*/
mrs x26, far_el1
- enable_daif
+ enable_da_f
+#ifdef CONFIG_TRACE_IRQFLAGS
+ bl trace_hardirqs_off
+#endif
ct_user_exit
mov x0, x26
mov x1, x25
mov x2, sp
- bl do_mem_abort
+ bl do_el0_ia_bp_hardening
b ret_to_user
el0_fpsimd_acc:
/*
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 5203b6040cb6..0e671ddf4855 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -318,7 +318,6 @@ static void __do_user_fault(struct task_struct *tsk, unsigned long addr,
lsb = PAGE_SHIFT;
si.si_addr_lsb = lsb;
- arm64_apply_bp_hardening();
force_sig_info(sig, &si, tsk);
}
@@ -709,6 +708,23 @@ asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr,
arm64_notify_die("", regs, &info, esr);
}
+asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr,
+ unsigned int esr,
+ struct pt_regs *regs)
+{
+ /*
+ * We've taken an instruction abort from userspace and not yet
+ * re-enabled IRQs. If the address is a kernel address, apply
+ * BP hardening prior to enabling IRQs and pre-emption.
+ */
+ if (addr > TASK_SIZE)
+ arm64_apply_bp_hardening();
+
+ local_irq_enable();
+ do_mem_abort(addr, esr, regs);
+}
+
+
asmlinkage void __exception do_sp_pc_abort(unsigned long addr,
unsigned int esr,
struct pt_regs *regs)
next prev parent reply other threads:[~2018-01-08 14:26 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-05 13:12 [PATCH v2 00/11] arm64 kpti hardening and variant 2 workarounds Will Deacon
2018-01-05 13:12 ` [PATCH v2 01/11] arm64: use RET instruction for exiting the trampoline Will Deacon
2018-01-06 13:13 ` Ard Biesheuvel
2018-01-08 14:33 ` Will Deacon
2018-01-08 14:38 ` Ard Biesheuvel
2018-01-08 14:45 ` Will Deacon
2018-01-08 14:56 ` Ard Biesheuvel
2018-01-08 15:27 ` David Laight
2018-01-05 13:12 ` [PATCH v2 02/11] arm64: Kconfig: Reword UNMAP_KERNEL_AT_EL0 kconfig entry Will Deacon
2018-01-05 13:12 ` [PATCH v2 03/11] arm64: Take into account ID_AA64PFR0_EL1.CSV3 Will Deacon
2018-01-08 7:24 ` [v2,03/11] " Jayachandran C
2018-01-08 9:20 ` Marc Zyngier
2018-01-08 17:40 ` Jayachandran C
2018-01-08 17:51 ` Will Deacon
2018-01-08 18:22 ` Alan Cox
2018-01-09 4:06 ` Jayachandran C
2018-01-09 10:00 ` Will Deacon
2018-01-19 1:00 ` Jon Masters
2018-01-08 17:52 ` Marc Zyngier
2018-01-08 17:06 ` Will Deacon
2018-01-08 17:50 ` Jayachandran C
2018-01-05 13:12 ` [PATCH v2 04/11] arm64: cpufeature: Pass capability structure to ->enable callback Will Deacon
2018-01-05 13:12 ` [PATCH v2 05/11] drivers/firmware: Expose psci_get_version through psci_ops structure Will Deacon
2018-01-05 13:12 ` [PATCH v2 06/11] arm64: Move post_ttbr_update_workaround to C code Will Deacon
2018-01-05 13:12 ` [PATCH v2 07/11] arm64: Add skeleton to harden the branch predictor against aliasing attacks Will Deacon
2018-01-08 0:15 ` Jon Masters
2018-01-08 12:16 ` James Morse
2018-01-08 14:26 ` Will Deacon [this message]
2018-01-17 4:10 ` Yisheng Xie
2018-01-17 10:07 ` Will Deacon
2018-01-18 8:37 ` Yisheng Xie
2018-01-19 3:37 ` Li Kun
2018-01-19 14:28 ` Will Deacon
2018-01-22 6:52 ` Li Kun
2018-01-05 13:12 ` [PATCH v2 08/11] arm64: KVM: Use per-CPU vector when BP hardening is enabled Will Deacon
2018-01-05 13:12 ` [PATCH v2 09/11] arm64: KVM: Make PSCI_VERSION a fast path Will Deacon
2018-01-05 13:12 ` [PATCH v2 10/11] arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75 Will Deacon
2018-01-05 13:12 ` [PATCH v2 11/11] arm64: Implement branch predictor hardening for affected Cortex-A CPUs Will Deacon
2018-01-05 14:46 ` James Morse
2018-01-05 14:57 ` Marc Zyngier
2018-01-08 6:31 ` [v2, " Jayachandran C
2018-01-08 6:53 ` [PATCH 1/2] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs Jayachandran C
2018-01-08 6:53 ` [PATCH 2/2] arm64: Branch predictor hardening for Cavium ThunderX2 Jayachandran C
2018-01-08 16:46 ` Will Deacon
2018-01-08 17:19 ` Jayachandran C
2018-01-08 17:23 ` Will Deacon
2018-01-09 2:26 ` Jayachandran C
2018-01-09 9:53 ` Will Deacon
2018-01-09 12:47 ` [PATCH v2] " Jayachandran C
2018-01-16 21:50 ` Jon Masters
2018-01-16 21:52 ` Jon Masters
2018-01-16 23:45 ` Jayachandran C
2018-01-17 18:34 ` Jon Masters
2018-01-18 13:53 ` Will Deacon
2018-01-18 17:56 ` Jayachandran C
2018-01-18 18:27 ` Jon Masters
2018-01-18 23:28 ` Jayachandran C
2018-01-19 1:17 ` Jon Masters
2018-01-19 12:22 ` [PATCH v3 1/2] " Jayachandran C
2018-01-19 12:22 ` [PATCH v3 2/2] arm64: Turn on KPTI only on CPUs that need it Jayachandran C
2018-01-22 11:41 ` Will Deacon
2018-01-22 11:51 ` Ard Biesheuvel
2018-01-22 11:55 ` Will Deacon
2018-01-22 18:59 ` Jon Masters
2018-01-19 19:08 ` [PATCH v3 1/2] arm64: Branch predictor hardening for Cavium ThunderX2 Jon Masters
2018-01-22 11:33 ` Will Deacon
2018-01-22 19:00 ` Jon Masters
2018-01-23 9:51 ` Will Deacon
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